Lines Matching +full:ch3 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
40 "ti,gpo-config-1",
41 "ti,gpo-config-2",
42 "ti,gpo-config-3",
43 "ti,gpo-config-4",
47 { ADCX140_PAGE_SELECT, 0x00 },
48 { ADCX140_SW_RESET, 0x00 },
49 { ADCX140_SLEEP_CFG, 0x00 },
50 { ADCX140_SHDN_CFG, 0x05 },
51 { ADCX140_ASI_CFG0, 0x30 },
52 { ADCX140_ASI_CFG1, 0x00 },
53 { ADCX140_ASI_CFG2, 0x00 },
54 { ADCX140_ASI_CH1, 0x00 },
55 { ADCX140_ASI_CH2, 0x01 },
56 { ADCX140_ASI_CH3, 0x02 },
57 { ADCX140_ASI_CH4, 0x03 },
58 { ADCX140_ASI_CH5, 0x04 },
59 { ADCX140_ASI_CH6, 0x05 },
60 { ADCX140_ASI_CH7, 0x06 },
61 { ADCX140_ASI_CH8, 0x07 },
62 { ADCX140_MST_CFG0, 0x02 },
63 { ADCX140_MST_CFG1, 0x48 },
64 { ADCX140_ASI_STS, 0xff },
65 { ADCX140_CLK_SRC, 0x10 },
66 { ADCX140_PDMCLK_CFG, 0x40 },
67 { ADCX140_PDM_CFG, 0x00 },
68 { ADCX140_GPIO_CFG0, 0x22 },
69 { ADCX140_GPO_CFG0, 0x00 },
70 { ADCX140_GPO_CFG1, 0x00 },
71 { ADCX140_GPO_CFG2, 0x00 },
72 { ADCX140_GPO_CFG3, 0x00 },
73 { ADCX140_GPO_VAL, 0x00 },
74 { ADCX140_GPIO_MON, 0x00 },
75 { ADCX140_GPI_CFG0, 0x00 },
76 { ADCX140_GPI_CFG1, 0x00 },
77 { ADCX140_GPI_MON, 0x00 },
78 { ADCX140_INT_CFG, 0x00 },
79 { ADCX140_INT_MASK0, 0xff },
80 { ADCX140_INT_LTCH0, 0x00 },
81 { ADCX140_BIAS_CFG, 0x00 },
82 { ADCX140_CH1_CFG0, 0x00 },
83 { ADCX140_CH1_CFG1, 0x00 },
84 { ADCX140_CH1_CFG2, 0xc9 },
85 { ADCX140_CH1_CFG3, 0x80 },
86 { ADCX140_CH1_CFG4, 0x00 },
87 { ADCX140_CH2_CFG0, 0x00 },
88 { ADCX140_CH2_CFG1, 0x00 },
89 { ADCX140_CH2_CFG2, 0xc9 },
90 { ADCX140_CH2_CFG3, 0x80 },
91 { ADCX140_CH2_CFG4, 0x00 },
92 { ADCX140_CH3_CFG0, 0x00 },
93 { ADCX140_CH3_CFG1, 0x00 },
94 { ADCX140_CH3_CFG2, 0xc9 },
95 { ADCX140_CH3_CFG3, 0x80 },
96 { ADCX140_CH3_CFG4, 0x00 },
97 { ADCX140_CH4_CFG0, 0x00 },
98 { ADCX140_CH4_CFG1, 0x00 },
99 { ADCX140_CH4_CFG2, 0xc9 },
100 { ADCX140_CH4_CFG3, 0x80 },
101 { ADCX140_CH4_CFG4, 0x00 },
102 { ADCX140_CH5_CFG2, 0xc9 },
103 { ADCX140_CH5_CFG3, 0x80 },
104 { ADCX140_CH5_CFG4, 0x00 },
105 { ADCX140_CH6_CFG2, 0xc9 },
106 { ADCX140_CH6_CFG3, 0x80 },
107 { ADCX140_CH6_CFG4, 0x00 },
108 { ADCX140_CH7_CFG2, 0xc9 },
109 { ADCX140_CH7_CFG3, 0x80 },
110 { ADCX140_CH7_CFG4, 0x00 },
111 { ADCX140_CH8_CFG2, 0xc9 },
112 { ADCX140_CH8_CFG3, 0x80 },
113 { ADCX140_CH8_CFG4, 0x00 },
114 { ADCX140_DSP_CFG0, 0x01 },
115 { ADCX140_DSP_CFG1, 0x40 },
116 { ADCX140_DRE_CFG0, 0x7b },
117 { ADCX140_AGC_CFG0, 0xe7 },
118 { ADCX140_IN_CH_EN, 0xf0 },
119 { ADCX140_ASI_OUT_CH_EN, 0x00 },
120 { ADCX140_PWR_CFG, 0x00 },
121 { ADCX140_DEV_STS0, 0x00 },
122 { ADCX140_DEV_STS1, 0x80 },
127 .range_min = 0,
130 .selector_mask = 0xff,
131 .selector_shift = 0,
132 .window_start = 0,
162 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
163 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
165 /* ADC gain. From 0 to 42 dB in 1 dB steps */
166 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
168 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
169 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
171 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
173 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
174 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
176 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
179 "Linear Phase", "Low Latency", "Ultra-low Latency"
193 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
220 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
315 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
317 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
319 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
321 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
323 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
325 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
327 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
329 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
332 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
334 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
336 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
338 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
341 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
345 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
346 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
347 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
348 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
371 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
372 &adcx140_output_mixer_controls[0],
376 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
378 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
380 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
382 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
386 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
388 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
390 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
392 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
395 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
397 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
399 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
401 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
404 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
407 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
409 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
410 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
411 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
412 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
414 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
415 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
416 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
417 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
418 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
419 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
420 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
421 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
424 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
426 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
428 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
430 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
433 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
435 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
437 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
439 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
442 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
445 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
447 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
449 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
451 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
454 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
456 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
458 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
460 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
463 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
466 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
498 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in adcx140_phase_calib_info()
606 uinfo->count = 1; in adcx140_phase_calib_info()
607 uinfo->value.integer.min = 0; in adcx140_phase_calib_info()
608 uinfo->value.integer.max = 1; in adcx140_phase_calib_info()
609 return 0; in adcx140_phase_calib_info()
619 value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0; in adcx140_phase_calib_get()
622 return 0; in adcx140_phase_calib_get()
632 bool v = value->value.integer.value[0] ? true : false; in adcx140_phase_calib_put()
634 if (adcx140->phase_calib_on != v) { in adcx140_phase_calib_put()
635 adcx140->phase_calib_on = v; in adcx140_phase_calib_put()
638 return 0; in adcx140_phase_calib_put()
642 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
644 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
646 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
648 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
651 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
653 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
656 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
658 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
662 0, 0xff, 0, dig_vol_tlv),
664 0, 0xff, 0, dig_vol_tlv),
665 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
666 0, 0xff, 0, dig_vol_tlv),
668 0, 0xff, 0, dig_vol_tlv),
670 0, 0xff, 0, dig_vol_tlv),
672 0, 0xff, 0, dig_vol_tlv),
674 0, 0xff, 0, dig_vol_tlv),
676 0, 0xff, 0, dig_vol_tlv),
682 int ret = 0; in adcx140_reset()
684 if (adcx140->gpio_reset) { in adcx140_reset()
685 gpiod_direction_output(adcx140->gpio_reset, 0); in adcx140_reset()
688 gpiod_direction_output(adcx140->gpio_reset, 1); in adcx140_reset()
690 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET, in adcx140_reset()
702 int pwr_ctrl = 0; in adcx140_pwr_ctrl()
703 int ret = 0; in adcx140_pwr_ctrl()
704 struct snd_soc_component *component = adcx140->component; in adcx140_pwr_ctrl()
709 if (adcx140->micbias_vg && power_state) in adcx140_pwr_ctrl()
713 ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB, in adcx140_pwr_ctrl()
714 adcx140->phase_calib_on ? 0x00 : 0x40); in adcx140_pwr_ctrl()
716 dev_err(component->dev, "%s: register write error %d\n", in adcx140_pwr_ctrl()
720 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG, in adcx140_pwr_ctrl()
728 struct snd_soc_component *component = dai->component; in adcx140_hw_params()
730 u8 data = 0; in adcx140_hw_params()
746 dev_err(component->dev, "%s: Unsupported width %d\n", in adcx140_hw_params()
748 return -EINVAL; in adcx140_hw_params()
758 return 0; in adcx140_hw_params()
764 struct snd_soc_component *component = codec_dai->component; in adcx140_set_dai_fmt()
766 u8 iface_reg1 = 0; in adcx140_set_dai_fmt()
767 u8 iface_reg2 = 0; in adcx140_set_dai_fmt()
768 int offset = 0; in adcx140_set_dai_fmt()
779 dev_err(component->dev, "Invalid DAI clock provider\n"); in adcx140_set_dai_fmt()
780 return -EINVAL; in adcx140_set_dai_fmt()
799 dev_err(component->dev, "Invalid DAI interface format\n"); in adcx140_set_dai_fmt()
800 return -EINVAL; in adcx140_set_dai_fmt()
815 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); in adcx140_set_dai_fmt()
816 return -EINVAL; in adcx140_set_dai_fmt()
822 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; in adcx140_set_dai_fmt()
840 return 0; in adcx140_set_dai_fmt()
847 struct snd_soc_component *component = codec_dai->component; in adcx140_set_dai_tdm_slot()
854 if (tx_mask != GENMASK(__fls(tx_mask), 0)) { in adcx140_set_dai_tdm_slot()
855 dev_err(component->dev, "Only lower adjacent slots are supported\n"); in adcx140_set_dai_tdm_slot()
856 return -EINVAL; in adcx140_set_dai_tdm_slot()
866 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); in adcx140_set_dai_tdm_slot()
867 return -EINVAL; in adcx140_set_dai_tdm_slot()
870 adcx140->slot_width = slot_width; in adcx140_set_dai_tdm_slot()
872 return 0; in adcx140_set_dai_tdm_slot()
884 u32 gpo_output_val = 0; in adcx140_configure_gpo()
888 for (i = 0; i < ADCX140_NUM_GPOS; i++) { in adcx140_configure_gpo()
889 ret = device_property_read_u32_array(adcx140->dev, in adcx140_configure_gpo()
896 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) { in adcx140_configure_gpo()
897 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1); in adcx140_configure_gpo()
898 return -EINVAL; in adcx140_configure_gpo()
902 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1); in adcx140_configure_gpo()
903 return -EINVAL; in adcx140_configure_gpo()
906 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT | in adcx140_configure_gpo()
908 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i, in adcx140_configure_gpo()
914 return 0; in adcx140_configure_gpo()
920 int gpio_count = 0; in adcx140_configure_gpio()
922 u32 gpio_output_val = 0; in adcx140_configure_gpio()
925 gpio_count = device_property_count_u32(adcx140->dev, in adcx140_configure_gpio()
926 "ti,gpio-config"); in adcx140_configure_gpio()
927 if (gpio_count <= 0) in adcx140_configure_gpio()
928 return 0; in adcx140_configure_gpio()
931 return -EINVAL; in adcx140_configure_gpio()
933 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config", in adcx140_configure_gpio()
938 if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) { in adcx140_configure_gpio()
939 dev_err(adcx140->dev, "GPIO config out of range\n"); in adcx140_configure_gpio()
940 return -EINVAL; in adcx140_configure_gpio()
944 dev_err(adcx140->dev, "GPIO drive out of range\n"); in adcx140_configure_gpio()
945 return -EINVAL; in adcx140_configure_gpio()
948 gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT in adcx140_configure_gpio()
951 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val); in adcx140_configure_gpio()
963 u32 pdm_edge_val = 0; in adcx140_codec_probe()
966 u32 gpi_input_val = 0; in adcx140_codec_probe()
971 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source", in adcx140_codec_probe()
975 adcx140->micbias_vg = false; in adcx140_codec_probe()
977 adcx140->micbias_vg = true; in adcx140_codec_probe()
980 ret = device_property_read_u32(adcx140->dev, "ti,vref-source", in adcx140_codec_probe()
986 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); in adcx140_codec_probe()
987 return -EINVAL; in adcx140_codec_probe()
996 if (adcx140->supply_areg == NULL) in adcx140_codec_probe()
999 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); in adcx140_codec_probe()
1001 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); in adcx140_codec_probe()
1008 pdm_count = device_property_count_u32(adcx140->dev, in adcx140_codec_probe()
1009 "ti,pdm-edge-select"); in adcx140_codec_probe()
1010 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) { in adcx140_codec_probe()
1011 ret = device_property_read_u32_array(adcx140->dev, in adcx140_codec_probe()
1012 "ti,pdm-edge-select", in adcx140_codec_probe()
1017 for (i = 0; i < pdm_count; i++) in adcx140_codec_probe()
1018 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i); in adcx140_codec_probe()
1020 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG, in adcx140_codec_probe()
1026 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config"); in adcx140_codec_probe()
1027 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) { in adcx140_codec_probe()
1028 ret = device_property_read_u32_array(adcx140->dev, in adcx140_codec_probe()
1029 "ti,gpi-config", in adcx140_codec_probe()
1037 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0, in adcx140_codec_probe()
1045 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1, in adcx140_codec_probe()
1059 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, in adcx140_codec_probe()
1063 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); in adcx140_codec_probe()
1065 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive"); in adcx140_codec_probe()
1067 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0, in adcx140_codec_probe()
1070 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret); in adcx140_codec_probe()
1096 return 0; in adcx140_set_bias_level()
1109 .idle_bias_on = 0,
1116 .name = "tlv320adcx140-codec",
1143 regulator_disable(adcx140->supply_areg); in adcx140_disable_regulator()
1151 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL); in adcx140_i2c_probe()
1153 return -ENOMEM; in adcx140_i2c_probe()
1155 adcx140->phase_calib_on = false; in adcx140_i2c_probe()
1156 adcx140->dev = &i2c->dev; in adcx140_i2c_probe()
1158 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, in adcx140_i2c_probe()
1160 if (IS_ERR(adcx140->gpio_reset)) in adcx140_i2c_probe()
1161 dev_info(&i2c->dev, "Reset GPIO not defined\n"); in adcx140_i2c_probe()
1163 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev, in adcx140_i2c_probe()
1165 if (IS_ERR(adcx140->supply_areg)) { in adcx140_i2c_probe()
1166 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER) in adcx140_i2c_probe()
1167 return -EPROBE_DEFER; in adcx140_i2c_probe()
1169 adcx140->supply_areg = NULL; in adcx140_i2c_probe()
1171 ret = regulator_enable(adcx140->supply_areg); in adcx140_i2c_probe()
1173 dev_err(adcx140->dev, "Failed to enable areg\n"); in adcx140_i2c_probe()
1177 ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140); in adcx140_i2c_probe()
1182 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap); in adcx140_i2c_probe()
1183 if (IS_ERR(adcx140->regmap)) { in adcx140_i2c_probe()
1184 ret = PTR_ERR(adcx140->regmap); in adcx140_i2c_probe()
1185 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in adcx140_i2c_probe()
1192 return devm_snd_soc_register_component(&i2c->dev, in adcx140_i2c_probe()
1198 { "tlv320adc3140", 0 },
1207 .name = "tlv320adcx140-codec",