1 // SPDX-License-Identifier: GPL-2.0-only
8 // Copyright (C) 2014-2018, Ambarella, Inc.
15 #include <dt-bindings/sound/tlv320adc3xxx.h>
33 #include <sound/soc-dapm.h>
54  * PLL modes, to be used for clk_id for set_sysclk callback.
57  * table, which is intended to be the PLL based one if there is more than one.
59  * Setting the clock source using simple-card (clocks or
60  * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.
63 #define ADC3XXX_PLL_ENABLE	1 /* Use PLL for clock generation */
64 #define ADC3XXX_PLL_BYPASS	2 /* Don't use PLL for clock generation */
78 /* 2-3 Reserved */
86 /* 9-17 Reserved */
93 /* 23-24 Reserved */
109 /* 39-41 Reserved */
122 /* 54-56 Reserved */
129 /* 63-79 Reserved */
152 /* 102-127 Reserved */
158 /* 1-25 Reserved */
160 /* 27-50 Reserved */
171 /* 63-127 Reserved */
194 /* PLL Enable bits */
231 /* PLL P/R bit offsets */
327 	int master;  member
482  * PLL and Clock settings.
483  * If p member is 0, PLL is not used.
484  * The order of the entries in this table have the PLL entries before
485  * the non-PLL entries, so that the PLL modes are preferred unless
486  * the PLL mode setting says otherwise.
508 	{ 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */
509 	{ 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */
529 		if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) ||  in adc3xxx_get_divs()
530 		    (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p))  in adc3xxx_get_divs()
533 		if (mode->rate == rate && mode->mclk == mclk)  in adc3xxx_get_divs()
537 	dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n",  in adc3xxx_get_divs()
539 	return -EINVAL;  in adc3xxx_get_divs()
545 	/* 10msec delay needed after PLL power-up to allow  in adc3xxx_pll_delay()
546 	 * PLL and dividers to stabilize (datasheet p13).  in adc3xxx_pll_delay()
556 	int numcoeff = kcontrol->private_value >> 16;  in adc3xxx_coefficient_info()
558 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;  in adc3xxx_coefficient_info()
559 	uinfo->count = numcoeff;  in adc3xxx_coefficient_info()
560 	uinfo->value.integer.min = 0;  in adc3xxx_coefficient_info()
561 	uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */  in adc3xxx_coefficient_info()
569 	int numcoeff  = kcontrol->private_value >> 16;  in adc3xxx_coefficient_get()
570 	int reg = kcontrol->private_value & 0xffff;  in adc3xxx_coefficient_get()
585 		ucontrol->value.integer.value[index] = value;  in adc3xxx_coefficient_get()
595 	int numcoeff  = kcontrol->private_value >> 16;  in adc3xxx_coefficient_put()
596 	int reg = kcontrol->private_value & 0xffff;  in adc3xxx_coefficient_put()
601 		unsigned int value = ucontrol->value.integer.value[index];  in adc3xxx_coefficient_put()
617 /* All on-chip filters have coefficients which are expressed in terms of
618  * 16 bit values, so represent them as strings of 16-bit integers.
646 	"-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV"
657 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);
658 static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);
659 /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */
667 	0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0),
668 	1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0),
669 	4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0),
670 	7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0));
672  * range (i.e. just before -32 dB) rather than the lowest, we need to resort
676 	0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0),
684 /* Input attenuation: -6 dB or 0 dB */
685 static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0);
728 			   ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv),
761 			   ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv),
763 	 * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and
764 	 * -0.4 dB drops about 0.12 dB on a specific chip.
889 	/* This refers to the generated BCLK in master mode. */
962 		return -EINVAL;  in adc3xxx_gpio_request()
970 		if (adc3xxx->gpio_cfg[offset] != 0 &&  in adc3xxx_gpio_request()
971 		    adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1)  in adc3xxx_gpio_request()
972 			return -EINVAL;  in adc3xxx_gpio_request()
978 		if (!adc3xxx->micbias_gpo[offset - ADC3XXX_GPIO_PINS])  in adc3xxx_gpio_request()
979 			return -EINVAL;  in adc3xxx_gpio_request()
993 		unsigned int micbias = offset - ADC3XXX_GPIO_PINS;  in adc3xxx_gpio_direction_out()
996 			vg = adc3xxx->micbias_vg[micbias];  in adc3xxx_gpio_direction_out()
999 		return regmap_update_bits(adc3xxx->regmap,  in adc3xxx_gpio_direction_out()
1006 	return regmap_update_bits(adc3xxx->regmap,  in adc3xxx_gpio_direction_out()
1036 		unsigned int micbias = offset - ADC3XXX_GPIO_PINS;  in adc3xxx_gpio_get()
1038 		ret = regmap_read(adc3xxx->regmap, ADC3XXX_MICBIAS_CTRL, &regval);  in adc3xxx_gpio_get()
1044 	ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], &regval);  in adc3xxx_gpio_get()
1063 	gpiochip_remove(&adc3xxx->gpio_chip);  in adc3xxx_free_gpio()
1072 	adc3xxx->gpio_chip = adc3xxx_gpio_chip;  in adc3xxx_init_gpio()
1073 	adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX;  in adc3xxx_init_gpio()
1074 	adc3xxx->gpio_chip.parent = adc3xxx->dev;  in adc3xxx_init_gpio()
1075 	adc3xxx->gpio_chip.base = -1;  in adc3xxx_init_gpio()
1077 	ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx);  in adc3xxx_init_gpio()
1079 		dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret);  in adc3xxx_init_gpio()
1086 		unsigned int cfg = adc3xxx->gpio_cfg[gpio];  in adc3xxx_init_gpio()
1089 			cfg--; /* actual value to use is stored +1 */  in adc3xxx_init_gpio()
1090 			regmap_update_bits(adc3xxx->regmap,  in adc3xxx_init_gpio()
1102 		if (adc3xxx->micbias_gpo[micbias])  in adc3xxx_init_gpio()
1105 			vg = adc3xxx->micbias_vg[micbias];  in adc3xxx_init_gpio()
1107 		regmap_update_bits(adc3xxx->regmap,  in adc3xxx_init_gpio()
1117 	struct device *dev = adc3xxx->dev;  in adc3xxx_parse_dt_gpio()
1118 	struct device_node *np = dev->of_node;  in adc3xxx_parse_dt_gpio()
1124 			return -EINVAL;  in adc3xxx_parse_dt_gpio()
1137 	struct device *dev = adc3xxx->dev;  in adc3xxx_parse_dt_micbias_gpo()
1138 	struct device_node *np = dev->of_node;  in adc3xxx_parse_dt_micbias_gpo()
1147 	struct device *dev = adc3xxx->dev;  in adc3xxx_parse_dt_micbias_vg()
1148 	struct device_node *np = dev->of_node;  in adc3xxx_parse_dt_micbias_vg()
1154 			return -EINVAL;  in adc3xxx_parse_dt_micbias_vg()
1165 		return -EINVAL;  in adc3xxx_parse_pll_mode()
1195 	struct snd_soc_component *component = dai->component;  in adc3xxx_hw_params()
1196 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);  in adc3xxx_hw_params()
1201 	i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk,  in adc3xxx_hw_params()
1202 			     params_rate(params), adc3xxx->pll_mode);  in adc3xxx_hw_params()
1226 		dev_err(component->dev, "Unsupported serial data format\n");  in adc3xxx_hw_params()
1227 		return -EINVAL;  in adc3xxx_hw_params()
1231 	if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */  in adc3xxx_hw_params()
1234 		if (!adc3xxx->use_pll) {  in adc3xxx_hw_params()
1237 			adc3xxx->use_pll = 1;  in adc3xxx_hw_params()
1241 		if (adc3xxx->use_pll) {  in adc3xxx_hw_params()
1244 			adc3xxx->use_pll = 0;  in adc3xxx_hw_params()
1270 		return "PLL auto";  in adc3xxx_pll_mode_text()
1272 		return "PLL enable";  in adc3xxx_pll_mode_text()
1274 		return "PLL bypass";  in adc3xxx_pll_mode_text()
1279 	return "PLL unknown";  in adc3xxx_pll_mode_text()
1285 	struct snd_soc_component *component = codec_dai->component;  in adc3xxx_set_dai_sysclk()
1289 	ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode);  in adc3xxx_set_dai_sysclk()
1293 	adc3xxx->sysclk = freq;  in adc3xxx_set_dai_sysclk()
1294 	dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n",  in adc3xxx_set_dai_sysclk()
1295 		freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode));  in adc3xxx_set_dai_sysclk()
1301 	struct snd_soc_component *component = codec_dai->component;  in adc3xxx_set_dai_fmt()
1305 	int master = 0;  in adc3xxx_set_dai_fmt()  local
1310 		master = 1;  in adc3xxx_set_dai_fmt()
1314 		master = 0;  in adc3xxx_set_dai_fmt()
1317 		dev_err(component->dev, "Invalid DAI clock setup\n");  in adc3xxx_set_dai_fmt()
1318 		return -EINVAL;  in adc3xxx_set_dai_fmt()
1342 		dev_err(component->dev, "Invalid DAI format\n");  in adc3xxx_set_dai_fmt()
1343 		return -EINVAL;  in adc3xxx_set_dai_fmt()
1347 	if (master && !adc3xxx->master)  in adc3xxx_set_dai_fmt()
1350 	else if (!master && adc3xxx->master)  in adc3xxx_set_dai_fmt()
1353 	adc3xxx->master = master;  in adc3xxx_set_dai_fmt()
1372 	.name = "tlv320adc3xxx-hifi",
1402 	struct device *dev = &i2c->dev;  in adc3xxx_i2c_probe()
1409 		return -ENOMEM;  in adc3xxx_i2c_probe()
1410 	adc3xxx->dev = dev;  in adc3xxx_i2c_probe()
1412 	adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);  in adc3xxx_i2c_probe()
1413 	if (IS_ERR(adc3xxx->rst_pin)) {  in adc3xxx_i2c_probe()
1414 		return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin),  in adc3xxx_i2c_probe()
1418 	adc3xxx->mclk = devm_clk_get(dev, NULL);  in adc3xxx_i2c_probe()
1419 	if (IS_ERR(adc3xxx->mclk)) {  in adc3xxx_i2c_probe()
1422 		 * directly or via the PLL, but the driver does not (yet), so  in adc3xxx_i2c_probe()
1427 		return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk),  in adc3xxx_i2c_probe()
1429 	} else if (adc3xxx->mclk) {  in adc3xxx_i2c_probe()
1430 		ret = clk_prepare_enable(adc3xxx->mclk);  in adc3xxx_i2c_probe()
1433 		dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk));  in adc3xxx_i2c_probe()
1437 	ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]);  in adc3xxx_i2c_probe()
1441 	ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]);  in adc3xxx_i2c_probe()
1445 	ret = adc3xxx_parse_dt_micbias_gpo(adc3xxx, "ti,micbias1-gpo", &adc3xxx->micbias_gpo[0]);  in adc3xxx_i2c_probe()
1449 	ret = adc3xxx_parse_dt_micbias_gpo(adc3xxx, "ti,micbias2-gpo", &adc3xxx->micbias_gpo[1]);  in adc3xxx_i2c_probe()
1453 	ret = adc3xxx_parse_dt_micbias_vg(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]);  in adc3xxx_i2c_probe()
1457 	ret = adc3xxx_parse_dt_micbias_vg(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]);  in adc3xxx_i2c_probe()
1461 	adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap);  in adc3xxx_i2c_probe()
1462 	if (IS_ERR(adc3xxx->regmap)) {  in adc3xxx_i2c_probe()
1463 		ret = PTR_ERR(adc3xxx->regmap);  in adc3xxx_i2c_probe()
1470 	adc3xxx->type = id->driver_data;  in adc3xxx_i2c_probe()
1473 	gpiod_set_value_cansleep(adc3xxx->rst_pin, 1);  in adc3xxx_i2c_probe()
1475 	gpiod_set_value_cansleep(adc3xxx->rst_pin, 0);  in adc3xxx_i2c_probe()
1490 	clk_disable_unprepare(adc3xxx->mclk);  in adc3xxx_i2c_probe()
1498 	if (adc3xxx->mclk)  in adc3xxx_i2c_remove()
1499 		clk_disable_unprepare(adc3xxx->mclk);  in adc3xxx_i2c_remove()
1501 	snd_soc_unregister_component(&client->dev);  in adc3xxx_i2c_remove()
1513 		   .name = "tlv320adc3xxx-codec",