Lines Matching +full:0 +full:x0c00
12 #define TFA9879_DEVICE_CONTROL 0x00
13 #define TFA9879_SERIAL_INTERFACE_1 0x01
14 #define TFA9879_PCM_IOM2_FORMAT_1 0x02
15 #define TFA9879_SERIAL_INTERFACE_2 0x03
16 #define TFA9879_PCM_IOM2_FORMAT_2 0x04
17 #define TFA9879_EQUALIZER_A1 0x05
18 #define TFA9879_EQUALIZER_A2 0x06
19 #define TFA9879_EQUALIZER_B1 0x07
20 #define TFA9879_EQUALIZER_B2 0x08
21 #define TFA9879_EQUALIZER_C1 0x09
22 #define TFA9879_EQUALIZER_C2 0x0a
23 #define TFA9879_EQUALIZER_D1 0x0b
24 #define TFA9879_EQUALIZER_D2 0x0c
25 #define TFA9879_EQUALIZER_E1 0x0d
26 #define TFA9879_EQUALIZER_E2 0x0e
27 #define TFA9879_BYPASS_CONTROL 0x0f
28 #define TFA9879_DYNAMIC_RANGE_COMPR 0x10
29 #define TFA9879_BASS_TREBLE 0x11
30 #define TFA9879_HIGH_PASS_FILTER 0x12
31 #define TFA9879_VOLUME_CONTROL 0x13
32 #define TFA9879_MISC_CONTROL 0x14
33 #define TFA9879_MISC_STATUS 0x15
36 #define TFA9879_INPUT_SEL_MASK 0x0010
38 #define TFA9879_OPMODE_MASK 0x0008
40 #define TFA9879_RESET_MASK 0x0002
42 #define TFA9879_POWERUP_MASK 0x0001
43 #define TFA9879_POWERUP_SHIFT 0
46 #define TFA9879_MONO_SEL_MASK 0x0c00
48 #define TFA9879_MONO_SEL_LEFT 0
51 #define TFA9879_I2S_FS_MASK 0x03c0
53 #define TFA9879_I2S_FS_8000 0
65 #define TFA9879_I2S_SET_MASK 0x0038
73 #define TFA9879_SCK_POL_MASK 0x0004
75 #define TFA9879_SCK_POL_NORMAL 0
77 #define TFA9879_I_MODE_MASK 0x0003
78 #define TFA9879_I_MODE_SHIFT 0
79 #define TFA9879_I_MODE_I2S 0
84 #define TFA9879_PCM_FS_MASK 0x0800
86 #define TFA9879_A_LAW_MASK 0x0400
88 #define TFA9879_PCM_COMP_MASK 0x0200
90 #define TFA9879_PCM_DL_MASK 0x0100
92 #define TFA9879_D1_SLOT_MASK 0x00f0
94 #define TFA9879_D2_SLOT_MASK 0x000f
95 #define TFA9879_D2_SLOT_SHIFT 0
98 #define TFA9879_T1_MASK 0x8000
100 #define TFA9879_K1M_MASK 0x7ff0
102 #define TFA9879_K1E_MASK 0x000f
103 #define TFA9879_K1E_SHIFT 0
106 #define TFA9879_T2_MASK 0x8000
108 #define TFA9879_K2M_MASK 0x7800
110 #define TFA9879_K2E_MASK 0x0700
112 #define TFA9879_K0_MASK 0x00fe
114 #define TFA9879_S_MASK 0x0001
115 #define TFA9879_S_SHIFT 0
118 #define TFA9879_L_OCP_MASK 0x00c0
120 #define TFA9879_L_OTP_MASK 0x0030
122 #define TFA9879_CLIPCTRL_MASK 0x0008
124 #define TFA9879_HPF_BP_MASK 0x0004
126 #define TFA9879_DRC_BP_MASK 0x0002
128 #define TFA9879_EQ_BP_MASK 0x0001
129 #define TFA9879_EQ_BP_SHIFT 0
132 #define TFA9879_AT_LVL_MASK 0xf000
134 #define TFA9879_AT_RATE_MASK 0x0f00
136 #define TFA9879_RL_LVL_MASK 0x00f0
138 #define TFA9879_RL_RATE_MASK 0x000f
139 #define TFA9879_RL_RATE_SHIFT 0
142 #define TFA9879_G_TRBLE_MASK 0x3e00
144 #define TFA9879_F_TRBLE_MASK 0x0180
146 #define TFA9879_G_BASS_MASK 0x007c
148 #define TFA9879_F_BASS_MASK 0x0003
149 #define TFA9879_F_BASS_SHIFT 0
152 #define TFA9879_HP_CTRL_MASK 0x00ff
153 #define TFA9879_HP_CTRL_SHIFT 0
156 #define TFA9879_ZR_CRSS_MASK 0x1000
158 #define TFA9879_VOL_MASK 0x00ff
159 #define TFA9879_VOL_SHIFT 0
162 #define TFA9879_DE_PHAS_MASK 0x0c00
164 #define TFA9879_H_MUTE_MASK 0x0200
166 #define TFA9879_S_MUTE_MASK 0x0100
168 #define TFA9879_P_LIM_MASK 0x00ff
169 #define TFA9879_P_LIM_SHIFT 0
172 #define TFA9879_PS_MASK 0x4000
174 #define TFA9879_PORA_MASK 0x2000
176 #define TFA9879_AMP_MASK 0x0600
178 #define TFA9879_IBP_2_MASK 0x0100
180 #define TFA9879_OFP_2_MASK 0x0080
182 #define TFA9879_UFP_2_MASK 0x0040
184 #define TFA9879_IBP_1_MASK 0x0020
186 #define TFA9879_OFP_1_MASK 0x0010
188 #define TFA9879_UFP_1_MASK 0x0008
190 #define TFA9879_OCPOKA_MASK 0x0004
192 #define TFA9879_OCPOKB_MASK 0x0002
194 #define TFA9879_OTPOK_MASK 0x0001
195 #define TFA9879_OTPOK_SHIFT 0