Lines Matching +full:96 +full:khz
629 * 0 to 96 we use pre-calculated values.
638 /* register value 0 => -96dB */ in avc_get_threshold()
640 ucontrol->value.integer.value[0] = 96; in avc_get_threshold()
641 ucontrol->value.integer.value[1] = 96; in avc_get_threshold()
662 * 0 to 96 we use pre-calculated values.
672 if (db < 0 || db > 96) in avc_put_threshold()
758 0, 96, 0, avc_get_threshold, avc_put_threshold,
888 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
900 * if frame clock is lower than 44.1 kHz, sample freq should be set to in sgtl5000_set_clock()
901 * 32 kHz or 44.1 kHz. in sgtl5000_set_clock()
954 * factor of freq = 96 kHz can only be 256, since mclk is in the range in sgtl5000_set_clock()
1176 * only support 8~48K + 96K,