Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0
3 * rt715.c -- rt715 ALSA SoC audio driver
28 #include <sound/soc-dapm.h>
111 ret = regmap_read(rt715->regmap, addr_l, r_val); in rt715_get_gain()
118 ret = regmap_read(rt715->regmap, addr_h, l_val); in rt715_get_gain()
123 /* For Verb-Set Amplifier Gain (Verb ID = 3h) */
131 (struct soc_mixer_control *)kcontrol->private_value; in rt715_set_amp_gain_put()
138 if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) { in rt715_set_amp_gain_put()
145 addr_h = mc->reg; in rt715_set_amp_gain_put()
146 addr_l = mc->rreg; in rt715_set_amp_gain_put()
148 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ in rt715_set_amp_gain_put()
155 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_amp_gain_put()
156 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
160 rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0]; in rt715_set_amp_gain_put()
162 val_ll = ((ucontrol->value.integer.value[0]) & 0x7f); in rt715_set_amp_gain_put()
163 if (val_ll > mc->max) in rt715_set_amp_gain_put()
164 val_ll = mc->max; in rt715_set_amp_gain_put()
169 rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1]; in rt715_set_amp_gain_put()
171 val_lr = ((ucontrol->value.integer.value[1]) & 0x7f); in rt715_set_amp_gain_put()
172 if (val_lr > mc->max) in rt715_set_amp_gain_put()
173 val_lr = mc->max; in rt715_set_amp_gain_put()
181 val_h = (1 << mc->shift) | (3 << 4); in rt715_set_amp_gain_put()
182 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
184 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
188 val_h = (1 << mc->shift) | (1 << 5); in rt715_set_amp_gain_put()
189 regmap_write(rt715->regmap, addr_h, in rt715_set_amp_gain_put()
192 val_h = (1 << mc->shift) | (1 << 4); in rt715_set_amp_gain_put()
193 regmap_write(rt715->regmap, addr_l, in rt715_set_amp_gain_put()
197 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ in rt715_set_amp_gain_put()
209 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_amp_gain_put()
210 regmap_write(rt715->regmap, in rt715_set_amp_gain_put()
221 (struct soc_mixer_control *)kcontrol->private_value; in rt715_set_amp_gain_get()
225 addr_h = mc->reg; in rt715_set_amp_gain_get()
226 addr_l = mc->rreg; in rt715_set_amp_gain_get()
227 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ in rt715_set_amp_gain_get()
234 if (mc->invert) { in rt715_set_amp_gain_get()
243 ucontrol->value.integer.value[0] = read_ll; in rt715_set_amp_gain_get()
244 ucontrol->value.integer.value[1] = read_rl; in rt715_set_amp_gain_get()
267 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i]) in rt715_set_main_switch_put()
277 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_main_switch_put()
278 regmap_write(rt715->regmap, in rt715_set_main_switch_put()
283 rt715->kctl_8ch_switch_ori[j * 2] = in rt715_set_main_switch_put()
284 ucontrol->value.integer.value[j * 2]; in rt715_set_main_switch_put()
285 val_ll = (!ucontrol->value.integer.value[j * 2]) << 7; in rt715_set_main_switch_put()
291 rt715->kctl_8ch_switch_ori[j * 2 + 1] = in rt715_set_main_switch_put()
292 ucontrol->value.integer.value[j * 2 + 1]; in rt715_set_main_switch_put()
293 val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7; in rt715_set_main_switch_put()
302 regmap_write(rt715->regmap, addr_h, in rt715_set_main_switch_put()
304 regmap_write(rt715->regmap, addr_l, in rt715_set_main_switch_put()
309 regmap_write(rt715->regmap, addr_h, in rt715_set_main_switch_put()
313 regmap_write(rt715->regmap, addr_l, in rt715_set_main_switch_put()
325 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_main_switch_put()
326 regmap_write(rt715->regmap, in rt715_set_main_switch_put()
350 ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80); in rt715_set_main_switch_get()
351 ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80); in rt715_set_main_switch_get()
375 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i]) in rt715_set_main_vol_put()
384 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_main_vol_put()
385 regmap_write(rt715->regmap, in rt715_set_main_vol_put()
390 rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2]; in rt715_set_main_vol_put()
391 val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f); in rt715_set_main_vol_put()
399 rt715->kctl_8ch_vol_ori[j * 2 + 1] = in rt715_set_main_vol_put()
400 ucontrol->value.integer.value[j * 2 + 1]; in rt715_set_main_vol_put()
401 val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f); in rt715_set_main_vol_put()
411 regmap_write(rt715->regmap, addr_h, in rt715_set_main_vol_put()
413 regmap_write(rt715->regmap, addr_l, in rt715_set_main_vol_put()
418 regmap_write(rt715->regmap, addr_h, in rt715_set_main_vol_put()
422 regmap_write(rt715->regmap, addr_l, in rt715_set_main_vol_put()
434 if (dapm->bias_level <= SND_SOC_BIAS_STANDBY) in rt715_set_main_vol_put()
435 regmap_write(rt715->regmap, in rt715_set_main_vol_put()
459 ucontrol->value.integer.value[i * 2] = read_ll & 0x7f; in rt715_set_main_vol_get()
460 ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f; in rt715_set_main_vol_get()
466 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
472 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in rt715_switch_info()
473 uinfo->count = 8; in rt715_switch_info()
474 uinfo->value.integer.min = 0; in rt715_switch_info()
475 uinfo->value.integer.max = 1; in rt715_switch_info()
482 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in rt715_vol_info()
483 uinfo->count = 8; in rt715_vol_info()
484 uinfo->value.integer.min = 0; in rt715_vol_info()
485 uinfo->value.integer.max = 0x3f; in rt715_vol_info()
560 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rt715_mux_get()
564 /* nid = e->reg, vid = 0xf01 */ in rt715_mux_get()
565 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; in rt715_mux_get()
566 ret = regmap_read(rt715->regmap, reg, &val); in rt715_mux_get()
568 dev_err(component->dev, "%s: sdw read failed: %d\n", in rt715_mux_get()
574 * The first two indices of ADC Mux 24/25 are routed to the same in rt715_mux_get()
575 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2. in rt715_mux_get()
578 if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0)) in rt715_mux_get()
579 val -= 1; in rt715_mux_get()
580 ucontrol->value.enumerated.item[0] = val; in rt715_mux_get()
593 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rt715_mux_put()
594 unsigned int *item = ucontrol->value.enumerated.item; in rt715_mux_put()
598 if (item[0] >= e->items) in rt715_mux_put()
599 return -EINVAL; in rt715_mux_put()
601 /* Verb ID = 0x701h, nid = e->reg */ in rt715_mux_put()
602 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; in rt715_mux_put()
604 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; in rt715_mux_put()
605 ret = regmap_read(rt715->regmap, reg, &val2); in rt715_mux_put()
607 dev_err(component->dev, "%s: sdw read failed: %d\n", in rt715_mux_put()
618 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; in rt715_mux_put()
619 regmap_write(rt715->regmap, reg, val); in rt715_mux_put()
640 * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
683 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum,
687 SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum,
691 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum,
695 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum,
707 SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
708 SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
709 SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
710 SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
711 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
713 SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
715 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
717 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
724 {"DP6TX", NULL, "ADC 09"},
725 {"DP6TX", NULL, "ADC 08"},
726 {"DP4TX", NULL, "ADC 07"},
727 {"DP4TX", NULL, "ADC 27"},
728 {"ADC 09", NULL, "ADC 22 Mux"},
729 {"ADC 08", NULL, "ADC 23 Mux"},
730 {"ADC 07", NULL, "ADC 24 Mux"},
731 {"ADC 27", NULL, "ADC 25 Mux"},
732 {"ADC 22 Mux", "MIC1", "MIC1"},
733 {"ADC 22 Mux", "MIC2", "MIC2"},
734 {"ADC 22 Mux", "LINE1", "LINE1"},
735 {"ADC 22 Mux", "LINE2", "LINE2"},
736 {"ADC 22 Mux", "DMIC1", "DMIC1"},
737 {"ADC 22 Mux", "DMIC2", "DMIC2"},
738 {"ADC 22 Mux", "DMIC3", "DMIC3"},
739 {"ADC 22 Mux", "DMIC4", "DMIC4"},
740 {"ADC 23 Mux", "MIC1", "MIC1"},
741 {"ADC 23 Mux", "MIC2", "MIC2"},
742 {"ADC 23 Mux", "LINE1", "LINE1"},
743 {"ADC 23 Mux", "LINE2", "LINE2"},
744 {"ADC 23 Mux", "DMIC1", "DMIC1"},
745 {"ADC 23 Mux", "DMIC2", "DMIC2"},
746 {"ADC 23 Mux", "DMIC3", "DMIC3"},
747 {"ADC 23 Mux", "DMIC4", "DMIC4"},
748 {"ADC 24 Mux", "MIC2", "MIC2"},
749 {"ADC 24 Mux", "DMIC1", "DMIC1"},
750 {"ADC 24 Mux", "DMIC2", "DMIC2"},
751 {"ADC 24 Mux", "DMIC3", "DMIC3"},
752 {"ADC 24 Mux", "DMIC4", "DMIC4"},
753 {"ADC 25 Mux", "MIC1", "MIC1"},
754 {"ADC 25 Mux", "DMIC1", "DMIC1"},
755 {"ADC 25 Mux", "DMIC2", "DMIC2"},
756 {"ADC 25 Mux", "DMIC3", "DMIC3"},
757 {"ADC 25 Mux", "DMIC4", "DMIC4"},
769 if (dapm->bias_level == SND_SOC_BIAS_STANDBY) { in rt715_set_bias_level()
770 regmap_write(rt715->regmap, in rt715_set_bias_level()
778 regmap_write(rt715->regmap, in rt715_set_bias_level()
786 dapm->bias_level = level; in rt715_set_bias_level()
795 if (!rt715->first_hw_init) in rt715_probe()
798 ret = pm_runtime_resume(component->dev); in rt715_probe()
799 if (ret < 0 && ret != -EACCES) in rt715_probe()
837 struct snd_soc_component *component = dai->component; in rt715_pcm_hw_params()
848 return -EINVAL; in rt715_pcm_hw_params()
850 if (!rt715->slave) in rt715_pcm_hw_params()
851 return -EINVAL; in rt715_pcm_hw_params()
855 switch (dai->id) { in rt715_pcm_hw_params()
858 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500); in rt715_pcm_hw_params()
862 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000); in rt715_pcm_hw_params()
865 dev_err(component->dev, "%s: Invalid DAI id %d\n", __func__, dai->id); in rt715_pcm_hw_params()
866 return -EINVAL; in rt715_pcm_hw_params()
869 retval = sdw_stream_add_slave(rt715->slave, &stream_config, in rt715_pcm_hw_params()
872 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); in rt715_pcm_hw_params()
878 /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */ in rt715_pcm_hw_params()
886 dev_err(component->dev, "%s: Unsupported sample rate %d\n", in rt715_pcm_hw_params()
888 return -EINVAL; in rt715_pcm_hw_params()
893 val |= (params_channels(params) - 1); in rt715_pcm_hw_params()
895 dev_err(component->dev, "%s: Unsupported channels %d\n", in rt715_pcm_hw_params()
897 return -EINVAL; in rt715_pcm_hw_params()
917 return -EINVAL; in rt715_pcm_hw_params()
920 regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val); in rt715_pcm_hw_params()
921 regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val); in rt715_pcm_hw_params()
922 regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val); in rt715_pcm_hw_params()
923 regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val); in rt715_pcm_hw_params()
931 struct snd_soc_component *component = dai->component; in rt715_pcm_hw_free()
936 if (!rt715->slave) in rt715_pcm_hw_free()
937 return -EINVAL; in rt715_pcm_hw_free()
939 sdw_stream_remove_slave(rt715->slave, sdw_stream); in rt715_pcm_hw_free()
956 .name = "rt715-aif1",
968 .name = "rt715-aif2",
994 clk_freq = (rt715->params.curr_dr_freq >> 1); in rt715_clock_config()
1016 return -EINVAL; in rt715_clock_config()
1019 regmap_write(rt715->regmap, 0xe0, value); in rt715_clock_config()
1020 regmap_write(rt715->regmap, 0xf0, value); in rt715_clock_config()
1033 return -ENOMEM; in rt715_init()
1036 rt715->slave = slave; in rt715_init()
1037 rt715->regmap = regmap; in rt715_init()
1038 rt715->sdw_regmap = sdw_regmap; in rt715_init()
1040 regcache_cache_only(rt715->regmap, true); in rt715_init()
1046 rt715->hw_init = false; in rt715_init()
1047 rt715->first_hw_init = false; in rt715_init()
1068 * fail with -EACCESS because of race conditions between card creation and enumeration in rt715_init()
1078 if (rt715->hw_init) in rt715_io_init()
1081 regcache_cache_only(rt715->regmap, false); in rt715_io_init()
1086 if (!rt715->first_hw_init) in rt715_io_init()
1088 pm_runtime_set_active(&slave->dev); in rt715_io_init()
1090 pm_runtime_get_noresume(&slave->dev); in rt715_io_init()
1092 rt715_reset(rt715->regmap); in rt715_io_init()
1095 regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080); in rt715_io_init()
1096 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080); in rt715_io_init()
1098 regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080); in rt715_io_init()
1099 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080); in rt715_io_init()
1102 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20); in rt715_io_init()
1103 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20); in rt715_io_init()
1104 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20); in rt715_io_init()
1105 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20); in rt715_io_init()
1107 regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10); in rt715_io_init()
1108 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10); in rt715_io_init()
1109 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10); in rt715_io_init()
1110 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10); in rt715_io_init()
1112 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0); in rt715_io_init()
1113 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11); in rt715_io_init()
1114 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1); in rt715_io_init()
1115 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81); in rt715_io_init()
1116 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1); in rt715_io_init()
1117 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11); in rt715_io_init()
1118 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1); in rt715_io_init()
1119 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81); in rt715_io_init()
1120 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0); in rt715_io_init()
1121 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11); in rt715_io_init()
1122 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1); in rt715_io_init()
1123 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81); in rt715_io_init()
1124 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1); in rt715_io_init()
1125 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11); in rt715_io_init()
1126 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1); in rt715_io_init()
1127 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81); in rt715_io_init()
1130 regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); in rt715_io_init()
1132 if (rt715->first_hw_init) in rt715_io_init()
1133 regcache_mark_dirty(rt715->regmap); in rt715_io_init()
1135 rt715->first_hw_init = true; in rt715_io_init()
1138 rt715->hw_init = true; in rt715_io_init()
1140 pm_runtime_mark_last_busy(&slave->dev); in rt715_io_init()
1141 pm_runtime_put_autosuspend(&slave->dev); in rt715_io_init()