42 	if (ret < 0) {  in rt715_index_write()
57 	if (ret < 0)  in rt715_index_write_nid()
70 	*value = 0;  in rt715_index_read_nid()
72 	if (ret < 0)  in rt715_index_read_nid()
86 	if (ret < 0)  in rt715_index_update_bits()
97 	regmap_write(regmap, RT715_FUNC_RESET, 0);  in rt715_reset()
112 	if (ret < 0)  in rt715_get_gain()
116 	val_h |= 0x20;  in rt715_get_gain()
119 	if (ret < 0)  in rt715_get_gain()
135 	unsigned int k_vol_changed = 0;  in rt715_set_amp_gain_put()
137 	for (i = 0; i < 2; i++) {  in rt715_set_amp_gain_put()
149 		val_h = 0x80;  in rt715_set_amp_gain_put()
151 		val_h = 0x0;  in rt715_set_amp_gain_put()
160 	rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0];  in rt715_set_amp_gain_put()
162 	val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);  in rt715_set_amp_gain_put()
166 	val_ll |= read_ll & 0x80;  in rt715_set_amp_gain_put()
171 	val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);  in rt715_set_amp_gain_put()
175 	val_lr |= read_rl & 0x80;  in rt715_set_amp_gain_put()
177 	for (i = 0; i < 3; i++) { /* retry 3 times at most */  in rt715_set_amp_gain_put()
198 			val_h = 0x80;  in rt715_set_amp_gain_put()
200 			val_h = 0x0;  in rt715_set_amp_gain_put()
228 		val_h = 0x80;  in rt715_set_amp_gain_get()
230 		val_h = 0x0;  in rt715_set_amp_gain_get()
236 		read_ll = !(read_ll & 0x80);  in rt715_set_amp_gain_get()
237 		read_rl = !(read_rl & 0x80);  in rt715_set_amp_gain_get()
240 		read_ll = read_ll & 0x7f;  in rt715_set_amp_gain_get()
241 		read_rl = read_rl & 0x7f;  in rt715_set_amp_gain_get()
243 	ucontrol->value.integer.value[0] = read_ll;  in rt715_set_amp_gain_get()
246 	return 0;  in rt715_set_amp_gain_get()
262 	unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;  in rt715_set_main_switch_put()
263 	unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0;  in rt715_set_main_switch_put()
266 	for (i = 0; i < 8; i++) {  in rt715_set_main_switch_put()
271 	for (j = 0; j < loop_cnt; j++) {  in rt715_set_main_switch_put()
287 		val_ll |= read_ll & 0x7f;  in rt715_set_main_switch_put()
295 		val_lr |= read_rl & 0x7f;  in rt715_set_main_switch_put()
297 		for (i = 0; i < 3; i++) { /* retry 3 times at most */  in rt715_set_main_switch_put()
316 			val_h = 0x0;  in rt715_set_main_switch_put()
342 	unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;  in rt715_set_main_switch_get()
345 	for (i = 0; i < loop_cnt; i++) {  in rt715_set_main_switch_get()
350 		ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80);  in rt715_set_main_switch_get()
351 		ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80);  in rt715_set_main_switch_get()
354 	return 0;  in rt715_set_main_switch_get()
370 	unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr;  in rt715_set_main_vol_put()
371 	unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0;  in rt715_set_main_vol_put()
372 	unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f;  in rt715_set_main_vol_put()
374 	for (i = 0; i < 8; i++) {  in rt715_set_main_vol_put()
379 	for (j = 0; j < loop_cnt; j++) {  in rt715_set_main_vol_put()
391 		val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f);  in rt715_set_main_vol_put()
395 		val_ll |= read_ll & 0x80;  in rt715_set_main_vol_put()
401 		val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f);  in rt715_set_main_vol_put()
405 		val_lr |= read_rl & 0x80;  in rt715_set_main_vol_put()
407 		for (i = 0; i < 3; i++) { /* retry 3 times at most */  in rt715_set_main_vol_put()
425 			val_h = 0x0;  in rt715_set_main_vol_put()
451 	unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4;  in rt715_set_main_vol_get()
454 	for (i = 0; i < loop_cnt; i++) {  in rt715_set_main_vol_get()
459 		ucontrol->value.integer.value[i * 2] = read_ll & 0x7f;  in rt715_set_main_vol_get()
460 		ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f;  in rt715_set_main_vol_get()
463 	return 0;  in rt715_set_main_vol_get()
466 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
467 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
474 	uinfo->value.integer.min = 0;  in rt715_switch_info()
476 	return 0;  in rt715_switch_info()
484 	uinfo->value.integer.min = 0;  in rt715_vol_info()
485 	uinfo->value.integer.max = 0x3f;  in rt715_vol_info()
486 	return 0;  in rt715_vol_info()
521 			RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
525 			RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
529 			RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
533 			RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
537 			RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
541 			RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
545 			RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
549 			RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
564 	/* nid = e->reg, vid = 0xf01 */  in rt715_mux_get()
567 	if (ret < 0) {  in rt715_mux_get()
575 	 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.  in rt715_mux_get()
578 	if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))  in rt715_mux_get()
580 	ucontrol->value.enumerated.item[0] = val;  in rt715_mux_get()
582 	return 0;  in rt715_mux_get()
595 	unsigned int val, val2 = 0, change, reg;  in rt715_mux_put()
598 	if (item[0] >= e->items)  in rt715_mux_put()
601 	/* Verb ID = 0x701h, nid = e->reg */  in rt715_mux_put()
602 	val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;  in rt715_mux_put()
606 	if (ret < 0) {  in rt715_mux_put()
613 		change = 0;  in rt715_mux_put()
623 						item[0], e, NULL);  in rt715_mux_put()
640  * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
645 	0,
669 	rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
672 	rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
675 	RT715_MUX_IN3, 0, 0xf,
679 	RT715_MUX_IN4, 0, 0xf,
707 	SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
708 	SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
709 	SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
710 	SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
711 	SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
713 	SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
715 	SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
717 	SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
719 	SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
720 	SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
787 	return 0;  in rt715_set_bias_level()
796 		return 0;  in rt715_probe()
799 	if (ret < 0 && ret != -EACCES)  in rt715_probe()
802 	return 0;  in rt715_probe()
823 	return 0;  in rt715_set_sdw_stream()
839 	struct sdw_stream_config stream_config = {0};  in rt715_pcm_hw_params()
840 	struct sdw_port_config port_config = {0};  in rt715_pcm_hw_params()
843 	unsigned int val = 0;  in rt715_pcm_hw_params()
858 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);  in rt715_pcm_hw_params()
862 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);  in rt715_pcm_hw_params()
877 	/* bit 14 0:48K 1:44.1K */  in rt715_pcm_hw_params()
878 	/* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */  in rt715_pcm_hw_params()
880 		val |= 0x40 << 8;  in rt715_pcm_hw_params()
883 		val |= 0x0 << 8;  in rt715_pcm_hw_params()
892 		/* bit 3:0 Number of Channel */  in rt715_pcm_hw_params()
905 		val |= (0x1 << 4);  in rt715_pcm_hw_params()
908 		val |= (0x2 << 4);  in rt715_pcm_hw_params()
911 		val |= (0x3 << 4);  in rt715_pcm_hw_params()
914 		val |= (0x4 << 4);  in rt715_pcm_hw_params()
940 	return 0;  in rt715_pcm_hw_free()
998 		value = 0x0;  in rt715_clock_config()
1001 		value = 0x1;  in rt715_clock_config()
1004 		value = 0x2;  in rt715_clock_config()
1007 		value = 0x3;  in rt715_clock_config()
1010 		value = 0x4;  in rt715_clock_config()
1013 		value = 0x5;  in rt715_clock_config()
1019 	regmap_write(rt715->regmap, 0xe0, value);  in rt715_clock_config()
1020 	regmap_write(rt715->regmap, 0xf0, value);  in rt715_clock_config()
1022 	return 0;  in rt715_clock_config()
1053 	if (ret < 0)  in rt715_init()
1071 	return 0;  in rt715_init()
1079 		return 0;  in rt715_io_init()
1095 	regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);  in rt715_io_init()
1096 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);  in rt715_io_init()
1098 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);  in rt715_io_init()
1099 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);  in rt715_io_init()
1102 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);  in rt715_io_init()
1103 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);  in rt715_io_init()
1104 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);  in rt715_io_init()
1105 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);  in rt715_io_init()
1107 	regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);  in rt715_io_init()
1108 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);  in rt715_io_init()
1109 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);  in rt715_io_init()
1110 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);  in rt715_io_init()
1112 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
1113 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1114 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1115 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1116 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
1117 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1118 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1119 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1120 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
1121 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1122 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1123 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1124 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
1125 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
1126 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
1127 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
1143 	return 0;  in rt715_io_init()