Lines Matching full:wclk

38 	.dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
2601 	 * Only accept to set wclk rate to 44.1k or 48kHz.  in rt5682s_wclk_recalc_rate()
2624 	 * Only accept to set wclk rate to 44.1k or 48kHz.  in rt5682s_wclk_round_rate()
2650 	 * Whether the wclk's parent clk (mclk) exists or not, please ensure  in rt5682s_wclk_set_rate()
2651 	 * it is fixed or set to 48MHz before setting wclk rate. It's a  in rt5682s_wclk_set_rate()
2659 			"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",  in rt5682s_wclk_set_rate()
2733 	 * BCLK rates are set as a multiplier of WCLK in HW.  in rt5682s_bclk_round_rate()
2734 	 * We don't allow changing the parent WCLK. We just do  in rt5682s_bclk_round_rate()
2735 	 * some rounding down based on the parent WCLK rate  in rt5682s_bclk_round_rate()
2799 			/* Make MCLK the parent of WCLK */  in rt5682s_register_dai_clks()
2809 			/* Make WCLK the parent of BCLK */  in rt5682s_register_dai_clks()