Lines Matching +full:dmic2 +full:- +full:data +full:- +full:pin
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
26 #include <sound/soc-dapm.h>
887 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
888 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
890 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
891 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
907 /* Interface data select */
1029 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1061 return -EINVAL; in rt5665_sel_asrc_clk_src()
1158 * rt5665_headset_detect - Detect headset.
1176 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, in rt5665_headset_detect()
1179 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1181 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1184 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val); in rt5665_headset_detect()
1187 regmap_read(rt5665->regmap, RT5665_GPIO_STA, in rt5665_headset_detect()
1192 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_headset_detect()
1194 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424); in rt5665_headset_detect()
1195 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048); in rt5665_headset_detect()
1196 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291); in rt5665_headset_detect()
1200 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component, in rt5665_headset_detect()
1203 sar_hs_type = rt5665->pdata.sar_hs_type ? in rt5665_headset_detect()
1204 rt5665->pdata.sar_hs_type : 729; in rt5665_headset_detect()
1206 if (rt5665->sar_adc_value > sar_hs_type) { in rt5665_headset_detect()
1207 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_headset_detect()
1210 rt5665->jack_type = SND_JACK_HEADPHONE; in rt5665_headset_detect()
1211 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, in rt5665_headset_detect()
1213 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, in rt5665_headset_detect()
1219 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291); in rt5665_headset_detect()
1220 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0); in rt5665_headset_detect()
1223 if (rt5665->jack_type == SND_JACK_HEADSET) in rt5665_headset_detect()
1225 rt5665->jack_type = 0; in rt5665_headset_detect()
1228 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type); in rt5665_headset_detect()
1229 return rt5665->jack_type; in rt5665_headset_detect()
1232 static irqreturn_t rt5665_irq(int irq, void *data) in rt5665_irq() argument
1234 struct rt5665_priv *rt5665 = data; in rt5665_irq()
1237 &rt5665->jack_detect_work, msecs_to_jiffies(250)); in rt5665_irq()
1247 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) { in rt5665_jd_check_handler()
1249 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jd_check_handler()
1251 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jd_check_handler()
1256 schedule_delayed_work(&rt5665->jd_check_work, 500); in rt5665_jd_check_handler()
1261 struct snd_soc_jack *hs_jack, void *data) in rt5665_set_jack_detect() argument
1265 switch (rt5665->pdata.jd_src) { in rt5665_set_jack_detect()
1267 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_set_jack_detect()
1269 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL, in rt5665_set_jack_detect()
1271 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2, in rt5665_set_jack_detect()
1273 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8); in rt5665_set_jack_detect()
1280 dev_warn(component->dev, "Wrong JD source\n"); in rt5665_set_jack_detect()
1284 rt5665->hs_jack = hs_jack; in rt5665_set_jack_detect()
1295 while (!rt5665->component) { in rt5665_jack_detect_handler()
1300 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { in rt5665_jack_detect_handler()
1305 while (!rt5665->calibration_done) { in rt5665_jack_detect_handler()
1310 mutex_lock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1312 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010; in rt5665_jack_detect_handler()
1315 if (rt5665->jack_type == 0) { in rt5665_jack_detect_handler()
1317 rt5665->jack_type = in rt5665_jack_detect_handler()
1318 rt5665_headset_detect(rt5665->component, 1); in rt5665_jack_detect_handler()
1321 rt5665->jack_type = SND_JACK_HEADSET; in rt5665_jack_detect_handler()
1322 btn_type = rt5665_button_detect(rt5665->component); in rt5665_jack_detect_handler()
1334 rt5665->jack_type |= SND_JACK_BTN_0; in rt5665_jack_detect_handler()
1339 rt5665->jack_type |= SND_JACK_BTN_1; in rt5665_jack_detect_handler()
1344 rt5665->jack_type |= SND_JACK_BTN_2; in rt5665_jack_detect_handler()
1349 rt5665->jack_type |= SND_JACK_BTN_3; in rt5665_jack_detect_handler()
1355 dev_err(rt5665->component->dev, in rt5665_jack_detect_handler()
1363 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0); in rt5665_jack_detect_handler()
1366 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type, in rt5665_jack_detect_handler()
1371 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 | in rt5665_jack_detect_handler()
1373 schedule_delayed_work(&rt5665->jd_check_work, 0); in rt5665_jack_detect_handler()
1375 cancel_delayed_work_sync(&rt5665->jd_check_work); in rt5665_jack_detect_handler()
1377 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_jack_detect_handler()
1466 * set_dmic_clk - Set parameter of dmic.
1478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1482 pd = rl6231_get_pre_div(rt5665->regmap, in set_dmic_clk()
1484 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd); in set_dmic_clk()
1487 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1498 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_charge_pump_event()
1522 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_sys_clk_from_pll()
1536 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in is_using_asrc()
1538 switch (w->shift) { in is_using_asrc()
1837 /*MX-17 [6:4], MX-17 [2:0]*/
1857 /*MX-1B [6:4], MX-1B [2:0]*/
1877 /* MX-26 [13] [5] */
1897 /* MX-26 [11:10] [3:2] */
1917 /* MX-26 [12] [4] */
1937 /* MX-26 [8] */
1939 "DMIC1", "DMIC2"
1949 /* MX-26 [9] */
1961 /* MX-26 [1:0] */
1974 /* MX-27 [12] */
1988 /* MX-27 [13] */
2000 /* MX-27 [9][1]*/
2020 /* MX-27 [11:10], MX-27 [3:2] */
2040 /* MX-27 [8] */
2042 "DMIC1 L", "DMIC2 L"
2053 /* MX-27 [4] */
2066 /* MX-27 [5] */
2079 /* MX-27 [0] */
2081 "DMIC1 R", "DMIC2 R"
2093 /* MX-28 [13] [5] */
2113 /* MX-28 [11:10] [3:2] */
2133 /* MX-28 [12] [4] */
2153 /* MX-28 [8] */
2155 "DMIC1", "DMIC2"
2165 /* MX-28 [9] */
2177 /* MX-28 [1] */
2190 /* MX-29 [11:10], MX-29 [9:8]*/
2210 /* MX-2D [13:12], MX-2D [9:8]*/
2230 /* MX-2D [5:4], MX-2D [1:0]*/
2250 /* MX-2E [5:4], MX-2E [0]*/
2269 /* Interface2 ADC Data Input*/
2270 /* MX-2F [14:12] */
2283 /* MX-2F [6:4] */
2296 /* Interface3 ADC Data Input*/
2297 /* MX-30 [6:4] */
2311 /* MX-31 [11:10] [9:8] */
2332 /* MX-7a[10] */
2344 /* MX-7a[9] */
2356 /* MX-7a[8] */
2368 /* MX-7b[10] */
2380 /* MX-7b[9] */
2392 /* MX-7b[8] */
2404 /* MX-7b[7] */
2416 /* MX-7a[4:0] MX-7b[4:0] */
2473 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_mono_event()
2505 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_hp_event()
2531 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_lout_event()
2571 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_set_verf()
2575 switch (w->shift) { in rt5665_set_verf()
2598 switch (w->shift) { in rt5665_set_verf()
2629 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5665_i2s_pin_event()
2632 switch (w->shift) { in rt5665_i2s_pin_event()
2750 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2981 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2983 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2985 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2987 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2989 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2991 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2993 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2995 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
3301 {"DMIC2", NULL, "DMIC L2"},
3302 {"DMIC2", NULL, "DMIC R2"},
3382 {"DMIC L2", NULL, "DMIC2 Power"},
3384 {"DMIC R2", NULL, "DMIC2 Power"},
3387 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3390 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3393 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3396 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3399 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3402 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3526 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3527 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3528 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3530 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3531 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3532 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3533 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3534 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3535 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3536 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3537 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3538 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3539 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3543 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3544 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3545 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3546 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3547 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3548 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3549 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3550 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3552 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3553 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3555 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3556 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3557 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3558 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3559 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3560 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3561 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3563 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3564 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3565 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3566 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3567 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3568 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3569 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3570 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3571 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3572 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3573 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3574 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3575 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3576 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3578 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3579 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3580 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3581 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3582 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3583 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3584 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3585 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3586 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3587 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3588 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3589 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3590 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3591 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3592 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3593 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3594 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3595 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3596 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3597 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3598 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3599 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3600 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3601 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3602 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3604 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3605 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3606 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3607 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3608 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3609 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3610 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3611 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3612 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3613 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3614 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3615 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3616 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3617 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3618 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3619 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3620 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3621 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3622 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3623 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3624 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3625 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3626 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3627 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3628 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3631 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3632 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3633 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3635 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3636 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3637 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3638 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3639 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3640 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3641 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3642 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3643 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3644 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3648 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3649 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3650 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3651 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3652 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3653 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3654 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3655 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3657 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3658 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3660 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3661 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3662 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3663 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3664 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3665 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3666 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3668 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3669 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3670 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3671 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3672 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3673 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3674 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3675 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3676 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3677 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3678 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3679 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3680 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3681 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3683 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3684 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3685 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3686 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3687 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3688 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3689 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3690 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3691 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3692 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3693 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3694 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3695 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3696 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3697 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3698 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3699 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3700 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3701 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3702 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3703 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3704 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3705 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3706 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3707 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3709 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3710 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3711 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3712 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3713 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3714 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3715 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3716 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3717 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3718 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3719 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3720 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3721 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3722 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3723 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3724 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3725 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3726 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3727 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3728 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3729 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3730 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3731 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3732 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3733 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3735 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3736 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3737 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3738 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3739 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3740 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3741 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3742 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3743 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3744 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3745 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3746 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3747 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3748 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3749 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3750 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3751 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3752 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3753 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3754 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3755 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3756 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3757 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3758 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3759 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3760 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3761 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3762 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3763 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3764 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3765 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3766 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
4051 struct snd_soc_component *component = dai->component; in rt5665_set_tdm_slot()
4073 return -EINVAL; in rt5665_set_tdm_slot()
4092 return -EINVAL; in rt5665_set_tdm_slot()
4107 struct snd_soc_component *component = dai->component; in rt5665_hw_params()
4112 rt5665->lrck[dai->id] = params_rate(params); in rt5665_hw_params()
4113 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]); in rt5665_hw_params()
4115 dev_warn(component->dev, "Force using PLL"); in rt5665_hw_params()
4117 rt5665->sysclk, rt5665->lrck[dai->id] * 512); in rt5665_hw_params()
4119 rt5665->lrck[dai->id] * 512, 0); in rt5665_hw_params()
4124 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5665_hw_params()
4125 return -EINVAL; in rt5665_hw_params()
4128 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt5665_hw_params()
4129 rt5665->lrck[dai->id], pre_div, dai->id); in rt5665_hw_params()
4147 return -EINVAL; in rt5665_hw_params()
4150 switch (dai->id) { in rt5665_hw_params()
4178 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_hw_params()
4179 return -EINVAL; in rt5665_hw_params()
4185 switch (rt5665->lrck[dai->id]) { in rt5665_hw_params()
4203 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_hw_params()
4207 if (rt5665->master[RT5665_AIF3]) { in rt5665_hw_params()
4217 struct snd_soc_component *component = dai->component; in rt5665_set_dai_fmt()
4223 rt5665->master[dai->id] = 1; in rt5665_set_dai_fmt()
4227 rt5665->master[dai->id] = 0; in rt5665_set_dai_fmt()
4230 return -EINVAL; in rt5665_set_dai_fmt()
4240 return -EINVAL; in rt5665_set_dai_fmt()
4256 return -EINVAL; in rt5665_set_dai_fmt()
4259 switch (dai->id) { in rt5665_set_dai_fmt()
4278 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt5665_set_dai_fmt()
4279 return -EINVAL; in rt5665_set_dai_fmt()
4290 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src) in rt5665_set_component_sysclk()
4307 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5665_set_component_sysclk()
4308 return -EINVAL; in rt5665_set_component_sysclk()
4313 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) { in rt5665_set_component_sysclk()
4317 if (rt5665->master[RT5665_AIF3]) { in rt5665_set_component_sysclk()
4322 rt5665->sysclk = freq; in rt5665_set_component_sysclk()
4323 rt5665->sysclk_src = clk_id; in rt5665_set_component_sysclk()
4325 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5665_set_component_sysclk()
4338 if (source == rt5665->pll_src && freq_in == rt5665->pll_in && in rt5665_set_component_pll()
4339 freq_out == rt5665->pll_out) in rt5665_set_component_pll()
4343 dev_dbg(component->dev, "PLL disabled\n"); in rt5665_set_component_pll()
4345 rt5665->pll_in = 0; in rt5665_set_component_pll()
4346 rt5665->pll_out = 0; in rt5665_set_component_pll()
4370 dev_err(component->dev, "Unknown PLL Source %d\n", source); in rt5665_set_component_pll()
4371 return -EINVAL; in rt5665_set_component_pll()
4376 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5665_set_component_pll()
4380 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt5665_set_component_pll()
4390 rt5665->pll_in = freq_in; in rt5665_set_component_pll()
4391 rt5665->pll_out = freq_out; in rt5665_set_component_pll()
4392 rt5665->pll_src = source; in rt5665_set_component_pll()
4399 struct snd_soc_component *component = dai->component; in rt5665_set_bclk_ratio()
4402 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); in rt5665_set_bclk_ratio()
4404 rt5665->bclk[dai->id] = ratio; in rt5665_set_bclk_ratio()
4407 switch (dai->id) { in rt5665_set_bclk_ratio()
4432 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4437 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4439 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4441 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC, in rt5665_set_bias_level()
4445 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1, in rt5665_set_bias_level()
4447 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_set_bias_level()
4462 rt5665->component = component; in rt5665_probe()
4464 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100)); in rt5665_probe()
4473 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_remove()
4475 regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), rt5665->supplies); in rt5665_remove()
4483 regcache_cache_only(rt5665->regmap, true); in rt5665_suspend()
4484 regcache_mark_dirty(rt5665->regmap); in rt5665_suspend()
4492 regcache_cache_only(rt5665->regmap, false); in rt5665_resume()
4493 regcache_sync(rt5665->regmap); in rt5665_resume()
4515 .name = "rt5665-aif1_1",
4534 .name = "rt5665-aif1_2",
4546 .name = "rt5665-aif2_1",
4565 .name = "rt5665-aif2_2",
4584 .name = "rt5665-aif3",
4645 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4646 "realtek,in1-differential"); in rt5665_parse_dt()
4647 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4648 "realtek,in2-differential"); in rt5665_parse_dt()
4649 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4650 "realtek,in3-differential"); in rt5665_parse_dt()
4651 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node, in rt5665_parse_dt()
4652 "realtek,in4-differential"); in rt5665_parse_dt()
4654 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin", in rt5665_parse_dt()
4655 &rt5665->pdata.dmic1_data_pin); in rt5665_parse_dt()
4656 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin", in rt5665_parse_dt()
4657 &rt5665->pdata.dmic2_data_pin); in rt5665_parse_dt()
4658 of_property_read_u32(dev->of_node, "realtek,jd-src", in rt5665_parse_dt()
4659 &rt5665->pdata.jd_src); in rt5665_parse_dt()
4668 mutex_lock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4670 regcache_cache_bypass(rt5665->regmap, true); in rt5665_calibrate()
4672 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4673 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4674 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26); in rt5665_calibrate()
4675 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f); in rt5665_calibrate()
4676 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a); in rt5665_calibrate()
4677 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f); in rt5665_calibrate()
4678 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180); in rt5665_calibrate()
4679 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040); in rt5665_calibrate()
4680 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000); in rt5665_calibrate()
4681 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001); in rt5665_calibrate()
4682 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380); in rt5665_calibrate()
4683 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000); in rt5665_calibrate()
4684 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000); in rt5665_calibrate()
4685 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030); in rt5665_calibrate()
4686 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05); in rt5665_calibrate()
4687 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e); in rt5665_calibrate()
4689 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e); in rt5665_calibrate()
4690 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321); in rt5665_calibrate()
4692 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00); in rt5665_calibrate()
4695 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value); in rt5665_calibrate()
4703 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4704 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4711 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24); in rt5665_calibrate()
4714 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value); in rt5665_calibrate()
4722 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4723 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4730 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_calibrate()
4731 regcache_cache_bypass(rt5665->regmap, false); in rt5665_calibrate()
4733 regcache_mark_dirty(rt5665->regmap); in rt5665_calibrate()
4734 regcache_sync(rt5665->regmap); in rt5665_calibrate()
4736 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602); in rt5665_calibrate()
4737 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120); in rt5665_calibrate()
4740 rt5665->calibration_done = true; in rt5665_calibrate()
4741 mutex_unlock(&rt5665->calibrate_mutex); in rt5665_calibrate()
4749 while (!snd_soc_card_is_instantiated(rt5665->component->card)) { in rt5665_calibrate_handler()
4759 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev); in rt5665_i2c_probe()
4764 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv), in rt5665_i2c_probe()
4768 return -ENOMEM; in rt5665_i2c_probe()
4773 rt5665->pdata = *pdata; in rt5665_i2c_probe()
4775 rt5665_parse_dt(rt5665, &i2c->dev); in rt5665_i2c_probe()
4777 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++) in rt5665_i2c_probe()
4778 rt5665->supplies[i].supply = rt5665_supply_names[i]; in rt5665_i2c_probe()
4780 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies), in rt5665_i2c_probe()
4781 rt5665->supplies); in rt5665_i2c_probe()
4783 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); in rt5665_i2c_probe()
4787 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies), in rt5665_i2c_probe()
4788 rt5665->supplies); in rt5665_i2c_probe()
4790 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); in rt5665_i2c_probe()
4795 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, in rt5665_i2c_probe()
4796 "realtek,ldo1-en", in rt5665_i2c_probe()
4798 if (IS_ERR(rt5665->gpiod_ldo1_en)) { in rt5665_i2c_probe()
4799 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n"); in rt5665_i2c_probe()
4800 return PTR_ERR(rt5665->gpiod_ldo1_en); in rt5665_i2c_probe()
4806 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap); in rt5665_i2c_probe()
4807 if (IS_ERR(rt5665->regmap)) { in rt5665_i2c_probe()
4808 ret = PTR_ERR(rt5665->regmap); in rt5665_i2c_probe()
4809 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5665_i2c_probe()
4814 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val); in rt5665_i2c_probe()
4816 dev_err(&i2c->dev, in rt5665_i2c_probe()
4818 return -ENODEV; in rt5665_i2c_probe()
4821 regmap_read(rt5665->regmap, RT5665_RESET, &val); in rt5665_i2c_probe()
4824 rt5665->id = CODEC_5666; in rt5665_i2c_probe()
4828 rt5665->id = CODEC_5665; in rt5665_i2c_probe()
4832 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_probe()
4835 if (rt5665->pdata.in1_diff) in rt5665_i2c_probe()
4836 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4838 if (rt5665->pdata.in2_diff) in rt5665_i2c_probe()
4839 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2, in rt5665_i2c_probe()
4841 if (rt5665->pdata.in3_diff) in rt5665_i2c_probe()
4842 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4844 if (rt5665->pdata.in4_diff) in rt5665_i2c_probe()
4845 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4, in rt5665_i2c_probe()
4848 /* DMIC pin*/ in rt5665_i2c_probe()
4849 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL || in rt5665_i2c_probe()
4850 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) { in rt5665_i2c_probe()
4851 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4853 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4855 switch (rt5665->pdata.dmic1_data_pin) { in rt5665_i2c_probe()
4857 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4862 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4864 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4869 dev_dbg(&i2c->dev, "no DMIC1\n"); in rt5665_i2c_probe()
4873 switch (rt5665->pdata.dmic2_data_pin) { in rt5665_i2c_probe()
4875 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1, in rt5665_i2c_probe()
4880 regmap_update_bits(rt5665->regmap, in rt5665_i2c_probe()
4884 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1, in rt5665_i2c_probe()
4889 dev_dbg(&i2c->dev, "no DMIC2\n"); in rt5665_i2c_probe()
4895 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002); in rt5665_i2c_probe()
4896 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1, in rt5665_i2c_probe()
4899 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET, in rt5665_i2c_probe()
4902 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, in rt5665_i2c_probe()
4906 if (rt5665->id == CODEC_5666) { in rt5665_i2c_probe()
4907 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2, in rt5665_i2c_probe()
4909 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3, in rt5665_i2c_probe()
4914 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1, in rt5665_i2c_probe()
4918 INIT_DELAYED_WORK(&rt5665->jack_detect_work, in rt5665_i2c_probe()
4920 INIT_DELAYED_WORK(&rt5665->calibrate_work, in rt5665_i2c_probe()
4922 INIT_DELAYED_WORK(&rt5665->jd_check_work, in rt5665_i2c_probe()
4925 mutex_init(&rt5665->calibrate_mutex); in rt5665_i2c_probe()
4927 if (i2c->irq) { in rt5665_i2c_probe()
4928 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in rt5665_i2c_probe()
4932 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); in rt5665_i2c_probe()
4936 return devm_snd_soc_register_component(&i2c->dev, in rt5665_i2c_probe()
4945 regmap_write(rt5665->regmap, RT5665_RESET, 0); in rt5665_i2c_shutdown()