Lines Matching +full:6 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
179 #define RT5651_VOL_L_SFT 14
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
183 #define RT5651_VOL_R_SFT 6
200 #define RT5651_IN_DF2 (0x1 << 6)
201 #define RT5651_IN_SFT2 6
261 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
262 #define RT5651_ADC_L_BST_SFT 14
269 #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
270 #define RT5651_M_STO1_ADC_L1_SFT 14
281 #define RT5651_M_STO1_ADC_R1 (0x1 << 6)
282 #define RT5651_M_STO1_ADC_R1_SFT 6
287 #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
288 #define RT5651_M_STO2_ADC_L1_SFT 14
299 #define RT5651_M_STO2_ADC_R1 (0x1 << 6)
300 #define RT5651_M_STO2_ADC_R1_SFT 6
315 #define RT5651_M_IF1_DAC_L (0x1 << 14)
316 #define RT5651_M_IF1_DAC_L_SFT 14
319 #define RT5651_M_IF1_DAC_R (0x1 << 6)
320 #define RT5651_M_IF1_DAC_R_SFT 6
323 #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
324 #define RT5651_M_DAC_L1_MIXL_SFT 14
335 #define RT5651_M_DAC_R1_MIXR (0x1 << 6)
336 #define RT5651_M_DAC_R1_MIXR_SFT 6
349 #define RT5651_M_STO_DD_L1 (0x1 << 14)
350 #define RT5651_M_STO_DD_L1_SFT 14
361 #define RT5651_M_STO_DD_R1 (0x1 << 6)
362 #define RT5651_M_STO_DD_R1_SFT 6
377 #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
378 #define RT5651_STO_L_DAC_L_VOL_SFT 14
397 #define RT5651_TXDP_SRC_MASK (0x1 << 14)
398 #define RT5651_TXDP_SRC_SFT 14
399 #define RT5651_TXDP_SRC_NOR (0x0 << 14)
400 #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
403 #define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
404 #define RT5651_DAC_L2_SEL_SFT 14
405 #define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
406 #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
407 #define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
408 #define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
428 #define RT5651_RXDP_SEL_MASK (0x3 << 6)
429 #define RT5651_RXDP_SEL_SFT 6
430 #define RT5651_RXDP_SEL_NOR (0x0 << 6)
431 #define RT5651_RXDP_SEL_L2R (0x1 << 6)
432 #define RT5651_RXDP_SEL_R2L (0x2 << 6)
433 #define RT5651_RXDP_SEL_SWAP (0x3 << 6)
470 #define RT5651_M_PDM_L (0x1 << 14)
471 #define RT5651_M_PDM_L_SFT 14
478 #define RT5651_PDM_BUSY (0x1 << 6)
479 #define RT5651_PDM_BUSY_SFT 6
522 #define RT5651_M_IN2_L_RM_L (0x1 << 6)
523 #define RT5651_M_IN2_L_RM_L_SFT 6
550 #define RT5651_M_IN2_R_RM_R (0x1 << 6)
551 #define RT5651_M_IN2_R_RM_R_SFT 6
564 #define RT5651_M_DAC1_HM (0x1 << 14)
565 #define RT5651_M_DAC1_HM_SFT 14
572 #define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
573 #define RT5651_G_RM_L_SM_L_SFT 14
580 #define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
581 #define RT5651_G_OM_L_SM_L_SFT 6
594 #define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
595 #define RT5651_G_RM_R_SM_R_SFT 14
602 #define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
603 #define RT5651_G_OM_R_SM_R_SFT 6
618 #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
619 #define RT5651_M_DAC_L1_SPM_L_SFT 14
642 #define RT5651_M_DAC_L2_MM (0x1 << 14)
643 #define RT5651_M_DAC_L2_MM_SFT 14
672 #define RT5651_M_BST2_OM_L (0x1 << 6)
673 #define RT5651_M_BST2_OM_L_SFT 6
702 #define RT5651_M_BST2_OM_R (0x1 << 6)
703 #define RT5651_M_BST2_OM_R_SFT 6
716 #define RT5651_M_DAC_R1_LM (0x1 << 14)
717 #define RT5651_M_DAC_R1_LM_SFT 14
728 #define RT5651_PWR_I2S2 (0x1 << 14)
729 #define RT5651_PWR_I2S2_BIT 14
742 #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
743 #define RT5651_PWR_ADC_STO2_F_BIT 14
754 #define RT5651_PWR_FV1 (0x1 << 14)
755 #define RT5651_PWR_FV1_BIT 14
764 #define RT5651_PWR_HP_R (0x1 << 6)
765 #define RT5651_PWR_HP_R_BIT 6
783 #define RT5651_PWR_BST2 (0x1 << 14)
784 #define RT5651_PWR_BST2_BIT 14
807 #define RT5651_PWR_OM_R (0x1 << 14)
808 #define RT5651_PWR_OM_R_BIT 14
829 #define RT5651_PWR_IN2_R (0x1 << 6)
830 #define RT5651_PWR_IN2_R_BIT 6
934 #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
935 #define RT5651_TDM_MODE_SEL_SFT 14
936 #define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
937 #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
958 #define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
959 #define RT5651_TDM_I2S_CH2_SEL_SFT 6
960 #define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
961 #define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
962 #define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
963 #define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
988 #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
989 #define RT5651_TDM_CH_VAL_SEL_SFT 14
990 #define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
991 #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
1012 #define RT5651_M_TDM2_R (0x1 << 6)
1013 #define RT5651_M_TDM2_R_SFT 6
1062 #define RT5651_SCLK_SRC_MASK (0x3 << 14)
1063 #define RT5651_SCLK_SRC_SFT 14
1064 #define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1065 #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1066 #define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1115 #define RT5651_STO2_ASRC_EN (0x1 << 14)
1116 #define RT5651_STO2_ASRC_EN_SFT 14
1161 /*PLL tracking mode 6 (0x89) */
1202 #define RT5651_RSTN_MASK (0x1 << 6)
1203 #define RT5651_RSTN_SFT 6
1204 #define RT5651_RSTN_DIS (0x0 << 6)
1205 #define RT5651_RSTN_EN (0x1 << 6)
1258 #define RT5651_DIG_DP_MASK (0x1 << 6)
1259 #define RT5651_DIG_DP_SFT 6
1260 #define RT5651_DIG_DP_DIS (0x0 << 6)
1261 #define RT5651_DIG_DP_EN (0x1 << 6)
1280 #define RT5651_CP_FQ_96_KHZ 6
1297 #define RT5651_IB_HP_MASK (0x3 << 6)
1298 #define RT5651_IB_HP_SFT 6
1299 #define RT5651_IB_HP_125IL (0x0 << 6)
1300 #define RT5651_IB_HP_25IL (0x1 << 6)
1301 #define RT5651_IB_HP_5IL (0x2 << 6)
1302 #define RT5651_IB_HP_1IL (0x3 << 6)
1364 #define RT5651_EQ_UPD (0x1 << 14)
1365 #define RT5651_EQ_UPD_BIT 14
1378 #define RT5651_EQ_STA_HP2 (0x1 << 6)
1379 #define RT5651_EQ_STA_HP2_BIT 6
1402 #define RT5651_EQ_HPF2_MASK (0x1 << 6)
1403 #define RT5651_EQ_HPF2_SFT 6
1404 #define RT5651_EQ_HPF2_DIS (0x0 << 6)
1405 #define RT5651_EQ_HPF2_EN (0x1 << 6)
1443 #define RT5651_ALC_MASK (0x1 << 14)
1444 #define RT5651_ALC_SFT 14
1445 #define RT5651_ALC_DIS (0x0 << 14)
1446 #define RT5651_ALC_EN (0x1 << 14)
1483 #define RT5651_ALC_NG_MASK (0x1 << 6)
1484 #define RT5651_ALC_NG_SFT 6
1485 #define RT5651_ALC_NG_DIS (0x0 << 6)
1486 #define RT5651_ALC_NG_EN (0x1 << 6)
1524 #define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1525 #define RT5651_JD_SPR_TRG_SFT 6
1526 #define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1527 #define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1549 #define RT5651_JD3_INV (0x1 << 6)
1550 #define RT5651_JD3_INV_SFT 6
1571 #define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1572 #define RT5651_JD1_2_IRQ_EN_SFT 6
1597 #define RT5651_MB2_OC_P_MASK (0x1 << 6)
1606 #define RT5651_STA_JD2 (0x1 << 14)
1607 #define RT5651_STA_JD2_BIT 14
1622 #define RT5651_STA_GP3 (0x1 << 6)
1623 #define RT5651_STA_GP3_BIT 6
1634 #define RT5651_GP2_PIN_MASK (0x1 << 14)
1635 #define RT5651_GP2_PIN_SFT 14
1636 #define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1637 #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1650 #define RT5651_GP6_PIN_MASK (0x1 << 6)
1651 #define RT5651_GP6_PIN_SFT 6
1652 #define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1653 #define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1668 #define RT5651_GP5_DR_MASK (0x1 << 14)
1669 #define RT5651_GP5_DR_SFT 14
1670 #define RT5651_GP5_DR_IN (0x0 << 14)
1671 #define RT5651_GP5_DR_OUT (0x1 << 14)
1700 #define RT5651_GP3_P_MASK (0x1 << 6)
1701 #define RT5651_GP3_P_SFT 6
1702 #define RT5651_GP3_P_NOR (0x0 << 6)
1703 #define RT5651_GP3_P_INV (0x1 << 6)
1738 #define RT5651_GP8_P_MASK (0x1 << 6)
1739 #define RT5651_GP8_P_SFT 6
1740 #define RT5651_GP8_P_NOR (0x0 << 6)
1741 #define RT5651_GP8_P_INV (0x1 << 6)
1772 #define RT5651_SCB_MASK (0x1 << 14)
1773 #define RT5651_SCB_SFT 14
1774 #define RT5651_SCB_DIS (0x0 << 14)
1775 #define RT5651_SCB_EN (0x1 << 14)
1794 #define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1795 #define RT5651_M_BB_HPF_R_SFT 6
1802 #define RT5651_M_MP3_R_MASK (0x1 << 14)
1803 #define RT5651_M_MP3_R_SFT 14
1814 #define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1815 #define RT5651_M_MP3_ORG_L_SFT 6
1834 #define RT5651_3D_HP_MASK (0x1 << 14)
1835 #define RT5651_3D_HP_SFT 14
1836 #define RT5651_3D_HP_DIS (0x0 << 14)
1837 #define RT5651_3D_HP_EN (0x1 << 14)
1854 #define RT5651_M_3D_REVB_MASK (0x1 << 6)
1855 #define RT5651_M_3D_REVB_SFT 6
1866 #define RT5651_ZD_T_MASK (0x3 << 6)
1867 #define RT5651_ZD_T_SFT 6
1894 #define RT5651_HPD_RCV_MASK (0x7 << 6)
1895 #define RT5651_HPD_RCV_SFT 6
1942 #define RT5651_M_ZCD_OM_R (0x1 << 6)
2001 #define RT5651_HPF_FC_MASK (0x3f << 6)
2002 #define RT5651_HPF_FC_SFT 6
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2026 #define RT5651_DP_ATT_MASK (0x3 << 14)
2027 #define RT5651_DP_ATT_SFT 14