Lines Matching +full:3 +full:x3
261 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
263 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
265 #define RT5651_ADC_COMP_MASK (0x3 << 10)
307 #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
308 #define RT5651_STO2_ADC_R2_SRC_SFT 3
309 #define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
310 #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
341 #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
342 #define RT5651_DAC_R2_STO_R_VOL_SFT 3
367 #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
368 #define RT5651_STO_DD_R2_VOL_SFT 3
403 #define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
408 #define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
409 #define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
422 #define RT5651_RXDC_SEL_MASK (0x3 << 8)
427 #define RT5651_RXDC_SEL_SWAP (0x3 << 8)
428 #define RT5651_RXDP_SEL_MASK (0x3 << 6)
433 #define RT5651_RXDP_SEL_SWAP (0x3 << 6)
434 #define RT5651_TXDC_SEL_MASK (0x3 << 4)
439 #define RT5651_TXDC_SEL_SWAP (0x3 << 4)
440 #define RT5651_TXDP_SEL_MASK (0x3 << 2)
445 #define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
448 #define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
453 #define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
454 #define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
459 #define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
485 #define RT5651_PDM_DIV_MASK (0x3)
490 #define RT5651_PDM_DIV_4 3
526 #define RT5651_M_BST3_RM_L (0x1 << 3)
527 #define RT5651_M_BST3_RM_L_SFT 3
554 #define RT5651_M_BST3_RM_R (0x1 << 3)
555 #define RT5651_M_BST3_RM_R_SFT 3
572 #define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
574 #define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
576 #define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
578 #define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
580 #define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
586 #define RT5651_M_DAC_L1_SM_L (0x1 << 3)
587 #define RT5651_M_DAC_L1_SM_L_SFT 3
594 #define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
596 #define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
598 #define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
600 #define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
602 #define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
608 #define RT5651_M_DAC_R1_SM_R (0x1 << 3)
609 #define RT5651_M_DAC_R1_SM_R_SFT 3
669 /* Output Left Mixer Control 3 (0x4f) */
678 #define RT5651_M_RM_L_OM_L (0x1 << 3)
679 #define RT5651_M_RM_L_OM_L_SFT 3
699 /* Output Right Mixer Control 3 (0x52) */
708 #define RT5651_M_RM_R_OM_R (0x1 << 3)
709 #define RT5651_M_RM_R_OM_R_SFT 3
770 #define RT5651_PWR_FV2 (0x1 << 3)
771 #define RT5651_PWR_FV2_BIT 3
774 #define RT5651_PWR_LDO_DVO_MASK (0x3)
778 #define RT5651_PWR_LDO_DVO_1_3V 3
795 #define RT5651_PWR_BST3_OP2 (0x1 << 3)
796 #define RT5651_PWR_BST3_OP2_BIT 3
832 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
837 #define RT5651_I2S_O_CP_MASK (0x3 << 10)
842 #define RT5651_I2S_I_CP_MASK (0x3 << 8)
851 #define RT5651_I2S_DL_MASK (0x3 << 2)
856 #define RT5651_I2S_DL_8 (0x3 << 2)
857 #define RT5651_I2S_DF_MASK (0x3)
862 #define RT5651_I2S_DF_PCM_B (0x3)
870 #define RT5651_I2S_PD1_4 (0x3 << 12)
884 #define RT5651_I2S_PD2_4 (0x3 << 8)
889 #define RT5651_DAC_OSR_MASK (0x3 << 2)
894 #define RT5651_DAC_OSR_128_3 (0x3 << 2)
895 #define RT5651_ADC_OSR_MASK (0x3)
900 #define RT5651_ADC_OSR_128_3 (0x3)
921 #define RT5651_DMIC_1_DP_MASK (0x3 << 10)
938 #define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
943 #define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
944 #define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
949 #define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
958 #define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
963 #define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
964 #define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
969 #define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
970 #define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
975 #define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
976 #define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
981 #define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
1019 /* TDM Control 3 (0x79) */
1025 #define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1035 #define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1045 #define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1055 #define RT5651_CH4_R_SEL_SL3 (0x3)
1062 #define RT5651_SCLK_SRC_MASK (0x3 << 14)
1067 #define RT5651_PLL1_SRC_MASK (0x3 << 12)
1072 #define RT5651_PLL1_PD_MASK (0x1 << 3)
1073 #define RT5651_PLL1_PD_SFT 3
1074 #define RT5651_PLL1_PD_1 (0x0 << 3)
1075 #define RT5651_PLL1_PD_2 (0x1 << 3)
1133 #define RT5651_I2S2_R_D_MASK (0x1 << 3)
1134 #define RT5651_I2S2_R_D_SFT 3
1135 #define RT5651_I2S2_R_D_DIS (0x0 << 3)
1136 #define RT5651_I2S2_R_D_EN (0x1 << 3)
1137 #define RT5651_PRE_SCLK_MASK (0x3)
1143 /* PLL tracking mode 3 (0x85) */
1148 #define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1149 #define RT5651_G_ASRC_LP_SFT 3
1154 #define RT5651_FTK_PH_DET_MASK (0x3)
1159 #define RT5651_FTK_PH_DET_DIV8 (0x3)
1178 #define RT5651_HP_OC_TH_MASK (0x3 << 8)
1183 #define RT5651_HP_OC_TH_135 (0x3 << 8)
1214 #define RT5651_HP_CP_MASK (0x1 << 3)
1215 #define RT5651_HP_CP_SFT 3
1216 #define RT5651_HP_CP_PD (0x0 << 3)
1217 #define RT5651_HP_CP_PU (0x1 << 3)
1248 #define RT5651_MRES_MASK (0x3 << 8)
1253 #define RT5651_MRES_45MO (0x3 << 8)
1262 #define RT5651_DP_TH_MASK (0x3 << 4)
1265 /* Depop Mode Control 3 (0x90) */
1277 #define RT5651_CP_FQ_12_KHZ 3
1292 #define RT5651_PM_HP_MASK (0x3 << 8)
1297 #define RT5651_IB_HP_MASK (0x3 << 6)
1302 #define RT5651_IB_HP_1IL (0x3 << 6)
1317 #define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1338 #define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1345 #define RT5651_JD_M_PU (0x1 << 3)
1346 #define RT5651_JD_M_PU_SFT 3
1349 #define RT5651_JD_M_MODE_SEL_MASK (0x3)
1370 #define RT5651_EQ_DITH_MASK (0x3 << 8)
1375 #define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1384 #define RT5651_EQ_STA_BP3 (0x1 << 3)
1385 #define RT5651_EQ_STA_BP3_BIT 3
1414 #define RT5651_EQ_BPF3_MASK (0x1 << 3)
1415 #define RT5651_EQ_BPF3_SFT 3
1416 #define RT5651_EQ_BPF3_DIS (0x0 << 3)
1417 #define RT5651_EQ_BPF3_EN (0x1 << 3)
1455 #define RT5651_ALC_R_192K (0x3 << 5)
1469 #define RT5651_ALC_CPR_MASK (0x3 << 5)
1474 #define RT5651_ALC_CPR_1_8 (0x3 << 5)
1478 /* ALC Control 3 (0xb6) */
1500 #define RT5651_JD_GPIO3 (0x3 << 13)
1528 #define RT5651_JD_LO_MASK (0x1 << 3)
1529 #define RT5651_JD_LO_SFT 3
1530 #define RT5651_JD_LO_DIS (0x0 << 3)
1531 #define RT5651_JD_LO_EN (0x1 << 3)
1543 #define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1577 #define RT5651_JD2_IRQ_EN (0x1 << 3)
1578 #define RT5651_JD2_IRQ_EN_SFT 3
1598 #define RT5651_MB1_OC_CLR (0x1 << 3)
1599 #define RT5651_MB1_OC_CLR_SFT 3
1662 #define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1663 #define RT5651_GPIO_PDM_SEL_SFT 3
1664 #define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1665 #define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1712 #define RT5651_GP2_P_MASK (0x1 << 3)
1713 #define RT5651_GP2_P_SFT 3
1714 #define RT5651_GP2_P_NOR (0x0 << 3)
1715 #define RT5651_GP2_P_INV (0x1 << 3)
1729 /* GPIO Control 3 (0xc2) */
1750 #define RT5651_GP7_P_MASK (0x1 << 3)
1751 #define RT5651_GP7_P_SFT 3
1752 #define RT5651_GP7_P_NOR (0x0 << 3)
1753 #define RT5651_GP7_P_INV (0x1 << 3)
1787 #define RT5651_BB_CT_D (0x3 << 12)
1829 /* 3D HP Control 1 (0xd2) */
1842 #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1866 #define RT5651_ZD_T_MASK (0x3 << 6)
1868 #define RT5651_ZD_F_MASK (0x3 << 4)
1873 #define RT5651_ZD_F_UN (0x3 << 4)
1904 #define RT5651_CAL_MASK (0x1 << 3)
1905 #define RT5651_CAL_SFT 3
1906 #define RT5651_CAL_DIS (0x0 << 3)
1907 #define RT5651_CAL_EN (0x1 << 3)
1912 #define RT5651_CAL_P_MASK (0x3)
1959 #define RT5651_CLK_DET_EN (0x1 << 3)
1960 #define RT5651_CLK_DET_EN_SFT 3
1969 #define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1974 #define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1976 /* 3D Speaker Control (0x63) */
1981 #define RT5651_3D_SPK_M_MASK (0x3 << 13)
2000 /* Wind Noise Detection Control 3 (0x6e) */
2026 #define RT5651_DP_ATT_MASK (0x3 << 14)