Lines Matching +full:10 +full:- +full:14

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * rt5651.h  --  RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /*  I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
178 #define RT5651_VOL_L_MUTE			(0x1 << 14)
179 #define RT5651_VOL_L_SFT			14
239 #define RT5651_SEL_DAC_R2			(0x1 << 10)
242 #define RT5651_SEL_DAC_R2_SFT			10
261 #define RT5651_ADC_L_BST_MASK			(0x3 << 14)
262 #define RT5651_ADC_L_BST_SFT			14
265 #define RT5651_ADC_COMP_MASK			(0x3 << 10)
266 #define RT5651_ADC_COMP_SFT			10
269 #define RT5651_M_STO1_ADC_L1			(0x1 << 14)
270 #define RT5651_M_STO1_ADC_L1_SFT		14
287 #define RT5651_M_STO2_ADC_L1			(0x1 << 14)
288 #define RT5651_M_STO2_ADC_L1_SFT		14
315 #define RT5651_M_IF1_DAC_L			(0x1 << 14)
316 #define RT5651_M_IF1_DAC_L_SFT			14
323 #define RT5651_M_DAC_L1_MIXL			(0x1 << 14)
324 #define RT5651_M_DAC_L1_MIXL_SFT		14
349 #define RT5651_M_STO_DD_L1			(0x1 << 14)
350 #define RT5651_M_STO_DD_L1_SFT			14
357 #define RT5651_M_STO_DD_R2_L			(0x1 << 10)
358 #define RT5651_M_STO_DD_R2_L_SFT		10
377 #define RT5651_STO_L_DAC_L_VOL_MASK		(0x1 << 14)
378 #define RT5651_STO_L_DAC_L_VOL_SFT		14
385 #define RT5651_STO_R_DAC_R_VOL_MASK		(0x1 << 10)
386 #define RT5651_STO_R_DAC_R_VOL_SFT		10
397 #define RT5651_TXDP_SRC_MASK			(0x1 << 14)
398 #define RT5651_TXDP_SRC_SFT			14
399 #define RT5651_TXDP_SRC_NOR			(0x0 << 14)
400 #define RT5651_TXDP_SRC_DIV3			(0x1 << 14)
403 #define RT5651_DAC_L2_SEL_MASK			(0x3 << 14)
404 #define RT5651_DAC_L2_SEL_SFT			14
405 #define RT5651_DAC_L2_SEL_IF2			(0x0 << 14)
406 #define RT5651_DAC_L2_SEL_IF3			(0x1 << 14)
407 #define RT5651_DAC_L2_SEL_TXDC			(0x2 << 14)
408 #define RT5651_DAC_L2_SEL_BASS			(0x3 << 14)
418 #define RT5651_IF2_ADC_R_SEL_MASK		(0x1 << 10)
419 #define RT5651_IF2_ADC_R_SEL_SFT		10
420 #define RT5651_IF2_ADC_R_SEL_TXDP		(0x0 << 10)
421 #define RT5651_IF2_ADC_R_SEL_PASS		(0x1 << 10)
448 #define RT5651_IF2_DAC_SEL_MASK			(0x3 << 10)
449 #define RT5651_IF2_DAC_SEL_SFT			10
450 #define RT5651_IF2_DAC_SEL_NOR			(0x0 << 10)
451 #define RT5651_IF2_DAC_SEL_SWAP			(0x1 << 10)
452 #define RT5651_IF2_DAC_SEL_L2R			(0x2 << 10)
453 #define RT5651_IF2_DAC_SEL_R2L			(0x3 << 10)
470 #define RT5651_M_PDM_L				(0x1 << 14)
471 #define RT5651_M_PDM_L_SFT			14
495 #define RT5651_PDM_I2C_CMD_MASK			(0x1 << 10)
496 #define RT5651_PDM_I2C_CMD_R			(0x0 << 10)
497 #define RT5651_PDM_I2C_CMD_W			(0x1 << 10)
510 #define RT5651_G_LN_L1_RM_L_MASK		(0x7 << 10)
511 #define RT5651_G_IN_L1_RM_L_SFT			10
520 #define RT5651_G_OM_L_RM_L_MASK			(0x7 << 10)
521 #define RT5651_G_OM_L_RM_L_SFT			10
538 #define RT5651_G_IN1_R_RM_R_MASK		(0x7 << 10)
539 #define RT5651_G_IN1_R_RM_R_SFT			10
548 #define RT5651_G_OM_R_RM_R_MASK			(0x7 << 10)
549 #define RT5651_G_OM_R_RM_R_SFT			10
564 #define RT5651_M_DAC1_HM			(0x1 << 14)
565 #define RT5651_M_DAC1_HM_SFT			14
572 #define RT5651_G_RM_L_SM_L_MASK			(0x3 << 14)
573 #define RT5651_G_RM_L_SM_L_SFT			14
576 #define RT5651_G_DAC_L1_SM_L_MASK		(0x3 << 10)
577 #define RT5651_G_DAC_L1_SM_L_SFT		10
594 #define RT5651_G_RM_R_SM_R_MASK			(0x3 << 14)
595 #define RT5651_G_RM_R_SM_R_SFT			14
598 #define RT5651_G_DAC_R1_SM_R_MASK		(0x3 << 10)
599 #define RT5651_G_DAC_R1_SM_R_SFT		10
618 #define RT5651_M_DAC_L1_SPM_L			(0x1 << 14)
619 #define RT5651_M_DAC_L1_SPM_L_SFT		14
642 #define RT5651_M_DAC_L2_MM			(0x1 << 14)
643 #define RT5651_M_DAC_L2_MM_SFT			14
650 #define RT5651_G_MONOMIX_MASK			(0x1 << 10)
651 #define RT5651_G_MONOMIX_SFT			10
654 #define RT5651_G_BST2_OM_L_MASK			(0x7 << 10)
655 #define RT5651_G_BST2_OM_L_SFT			10
684 #define RT5651_G_BST2_OM_R_MASK			(0x7 << 10)
685 #define RT5651_G_BST2_OM_R_SFT			10
716 #define RT5651_M_DAC_R1_LM			(0x1 << 14)
717 #define RT5651_M_DAC_R1_LM_SFT			14
728 #define RT5651_PWR_I2S2				(0x1 << 14)
729 #define RT5651_PWR_I2S2_BIT			14
742 #define RT5651_PWR_ADC_STO2_F			(0x1 << 14)
743 #define RT5651_PWR_ADC_STO2_F_BIT		14
746 #define RT5651_PWR_DAC_STO2_F			(0x1 << 10)
747 #define RT5651_PWR_DAC_STO2_F_BIT		10
754 #define RT5651_PWR_FV1				(0x1 << 14)
755 #define RT5651_PWR_FV1_BIT			14
783 #define RT5651_PWR_BST2				(0x1 << 14)
784 #define RT5651_PWR_BST2_BIT			14
807 #define RT5651_PWR_OM_R				(0x1 << 14)
808 #define RT5651_PWR_OM_R_BIT			14
811 #define RT5651_PWR_RM_R				(0x1 << 10)
812 #define RT5651_PWR_RM_R_BIT			10
821 #define RT5651_PWR_HV_R				(0x1 << 10)
822 #define RT5651_PWR_HV_R_BIT			10
837 #define RT5651_I2S_O_CP_MASK			(0x3 << 10)
838 #define RT5651_I2S_O_CP_SFT			10
839 #define RT5651_I2S_O_CP_OFF			(0x0 << 10)
840 #define RT5651_I2S_O_CP_U_LAW			(0x1 << 10)
841 #define RT5651_I2S_O_CP_A_LAW			(0x2 << 10)
905 #define RT5651_ADHPF_EN				(0x1 << 10)
906 #define RT5651_ADHPF_EN_SFT			10
921 #define RT5651_DMIC_1_DP_MASK			(0x3 << 10)
922 #define RT5651_DMIC_1_DP_SFT			10
923 #define RT5651_DMIC_1_DP_GPIO6			(0x0 << 10)
924 #define RT5651_DMIC_1_DP_IN1P			(0x1 << 10)
925 #define RT5651_DMIC_2_DP_GPIO8			(0x2 << 10)
934 #define RT5651_TDM_MODE_SEL_MASK		(0x1 << 14)
935 #define RT5651_TDM_MODE_SEL_SFT			14
936 #define RT5651_TDM_MODE_SEL_NOR			(0x0 << 14)
937 #define RT5651_TDM_MODE_SEL_TDM			(0x1 << 14)
944 #define RT5651_TDM_CH_LEN_SEL_MASK		(0x3 << 10)
945 #define RT5651_TDM_CH_LEN_SEL_SFT		10
946 #define RT5651_TDM_CH_LEN_SEL_16		(0x0 << 10)
947 #define RT5651_TDM_CH_LEN_SEL_20		(0x1 << 10)
948 #define RT5651_TDM_CH_LEN_SEL_24		(0x2 << 10)
949 #define RT5651_TDM_CH_LEN_SEL_32		(0x3 << 10)
988 #define RT5651_TDM_CH_VAL_SEL_MASK		(0x1 << 14)
989 #define RT5651_TDM_CH_VAL_SEL_SFT		14
990 #define RT5651_TDM_CH_VAL_SEL_CH01		(0x0 << 14)
991 #define RT5651_TDM_CH_VAL_SEL_CH0123		(0x1 << 14)
1000 #define RT5651_TDM_END_EDGE_SEL_MASK		(0x1 << 10)
1001 #define RT5651_TDM_END_EDGE_SEL_SFT		10
1002 #define RT5651_TDM_END_EDGE_SEL_POS		(0x0 << 10)
1003 #define RT5651_TDM_END_EDGE_SEL_NEG		(0x1 << 10)
1062 #define RT5651_SCLK_SRC_MASK			(0x3 << 14)
1063 #define RT5651_SCLK_SRC_SFT			14
1064 #define RT5651_SCLK_SRC_MCLK			(0x0 << 14)
1065 #define RT5651_SCLK_SRC_PLL1			(0x1 << 14)
1066 #define RT5651_SCLK_SRC_RCCLK			(0x2 << 14)
1115 #define RT5651_STO2_ASRC_EN			(0x1 << 14)
1116 #define RT5651_STO2_ASRC_EN_SFT			14
1174 #define RT5651_HP_OVCD_MASK			(0x1 << 10)
1175 #define RT5651_HP_OVCD_SFT			10
1176 #define RT5651_HP_OVCD_DIS			(0x0 << 10)
1177 #define RT5651_HP_OVCD_EN			(0x1 << 10)
1244 #define RT5651_FAST_UPDN_MASK			(0x1 << 10)
1245 #define RT5651_FAST_UPDN_SFT			10
1246 #define RT5651_FAST_UPDN_DIS			(0x0 << 10)
1247 #define RT5651_FAST_UPDN_EN			(0x1 << 10)
1288 #define RT5651_OSW_R_MASK			(0x1 << 10)
1289 #define RT5651_OSW_R_SFT			10
1290 #define RT5651_OSW_R_DIS			(0x0 << 10)
1291 #define RT5651_OSW_R_EN				(0x1 << 10)
1336 #define RT5651_JD_PD				(0x1 << 10)
1337 #define RT5651_JD_PD_SFT			10
1364 #define RT5651_EQ_UPD				(0x1 << 14)
1365 #define RT5651_EQ_UPD_BIT			14
1443 #define RT5651_ALC_MASK				(0x1 << 14)
1444 #define RT5651_ALC_SFT				14
1445 #define RT5651_ALC_DIS				(0x0 << 14)
1446 #define RT5651_ALC_EN				(0x1 << 14)
1508 #define RT5651_JD_HP_TRG_MASK			(0x1 << 10)
1509 #define RT5651_JD_HP_TRG_SFT			10
1510 #define RT5651_JD_HP_TRG_LO			(0x0 << 10)
1511 #define RT5651_JD_HP_TRG_HI			(0x1 << 10)
1606 #define RT5651_STA_JD2				(0x1 << 14)
1607 #define RT5651_STA_JD2_BIT			14
1614 #define RT5651_STA_GP6				(0x1 << 10)
1615 #define RT5651_STA_GP6_BIT			10
1634 #define RT5651_GP2_PIN_MASK			(0x1 << 14)
1635 #define RT5651_GP2_PIN_SFT			14
1636 #define RT5651_GP2_PIN_GPIO2			(0x0 << 14)
1637 #define RT5651_GP2_PIN_DMIC1_SCL		(0x1 << 14)
1668 #define RT5651_GP5_DR_MASK			(0x1 << 14)
1669 #define RT5651_GP5_DR_SFT			14
1670 #define RT5651_GP5_DR_IN			(0x0 << 14)
1671 #define RT5651_GP5_DR_OUT			(0x1 << 14)
1684 #define RT5651_GP4_OUT_MASK			(0x1 << 10)
1685 #define RT5651_GP4_OUT_SFT			10
1686 #define RT5651_GP4_OUT_LO			(0x0 << 10)
1687 #define RT5651_GP4_OUT_HI			(0x1 << 10)
1772 #define RT5651_SCB_MASK				(0x1 << 14)
1773 #define RT5651_SCB_SFT				14
1774 #define RT5651_SCB_DIS				(0x0 << 14)
1775 #define RT5651_SCB_EN				(0x1 << 14)
1802 #define RT5651_M_MP3_R_MASK			(0x1 << 14)
1803 #define RT5651_M_MP3_R_SFT			14
1834 #define RT5651_3D_HP_MASK			(0x1 << 14)
1835 #define RT5651_3D_HP_SFT			14
1836 #define RT5651_3D_HP_DIS			(0x0 << 14)
1837 #define RT5651_3D_HP_EN				(0x1 << 14)
1844 #define RT5651_3D_HP_M_MASK			(0x1 << 10)
1845 #define RT5651_3D_HP_M_SFT			10
1846 #define RT5651_3D_HP_M_SUR			(0x0 << 10)
1847 #define RT5651_3D_HP_M_FRO			(0x1 << 10)
1886 #define RT5651_DC_CAL_M_MASK			(0x1 << 10)
1887 #define RT5651_DC_CAL_M_SFT			10
1888 #define RT5651_DC_CAL_M_NOR			(0x0 << 10)
1889 #define RT5651_DC_CAL_M_CAL			(0x1 << 10)
1935 #define RT5651_ZCD_MASK				(0x1 << 10)
1936 #define RT5651_ZCD_SFT				10
1937 #define RT5651_ZCD_PD				(0x0 << 10)
1938 #define RT5651_ZCD_PU				(0x1 << 10)
1995 #define RT5651_WND_FC_NW_MASK			(0x3f << 10)
1996 #define RT5651_WND_FC_NW_SFT			10
2015 #define RT5651_WND_WIND_MASK			(0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK			(0x1 << 12) /* Read-Only */
2026 #define RT5651_DP_ATT_MASK			(0x3 << 14)
2027 #define RT5651_DP_ATT_SFT			14
2028 #define RT5651_DP_SPK_MASK			(0x1 << 10)
2029 #define RT5651_DP_SPK_SFT			10
2030 #define RT5651_DP_SPK_DIS			(0x0 << 10)
2031 #define RT5651_DP_SPK_EN			(0x1 << 10)