Lines Matching +full:6 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
220 #define RT5645_VOL_L_SFT 14
223 #define RT5645_VOL_R_MUTE (0x1 << 6)
224 #define RT5645_VOL_R_SFT 6
236 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
248 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
255 #define RT5645_IN_DF2 (0x1 << 6)
256 #define RT5645_IN_SFT2 6
307 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
308 #define RT5645_STO1_ADC_L_BST_SFT 14
315 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
316 #define RT5645_MONO_ADC_L_BST_SFT 14
327 #define RT5645_M_ADC_L1 (0x1 << 14)
328 #define RT5645_M_ADC_L1_SFT 14
339 #define RT5645_M_ADC_R1 (0x1 << 6)
340 #define RT5645_M_ADC_R1_SFT 6
347 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
348 #define RT5645_M_MONO_ADC_L1_SFT 14
359 #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
360 #define RT5645_M_MONO_ADC_R1_SFT 6
375 #define RT5645_M_DAC1_L (0x1 << 14)
376 #define RT5645_M_DAC1_L_SFT 14
391 #define RT5645_M_DAC1_R (0x1 << 6)
392 #define RT5645_M_DAC1_R_SFT 6
395 #define RT5645_M_DAC_L1 (0x1 << 14)
396 #define RT5645_M_DAC_L1_SFT 14
409 #define RT5645_M_DAC_R1 (0x1 << 6)
410 #define RT5645_M_DAC_R1_SFT 6
425 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
426 #define RT5645_M_DAC_L1_MONO_L_SFT 14
437 #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
438 #define RT5645_M_DAC_R1_MONO_R_SFT 6
453 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
454 #define RT5645_STO_L_DAC_L_VOL_SFT 14
469 #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
470 #define RT5645_DAC_R2_DAC_L_VOL_SFT 6
491 #define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
492 #define RT5645_IF3_DAC_SEL_SFT 6
501 #define RT5645_M_PDM1_L (0x1 << 14)
502 #define RT5645_M_PDM1_L_SFT 14
516 #define RT5645_PDM1_BUSY (0x1 << 6)
538 #define RT5645_M_MM_L_RM_L (0x1 << 6)
539 #define RT5645_M_MM_L_RM_L_SFT 6
570 #define RT5645_M_MM_R_RM_R (0x1 << 6)
571 #define RT5645_M_MM_R_RM_R_SFT 6
600 #define RT5645_M_DAC1_HM (0x1 << 14)
601 #define RT5645_M_DAC1_HM_SFT 14
607 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
608 #define RT5645_G_RM_L_SM_L_SFT 14
615 #define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
616 #define RT5645_G_OM_L_SM_L_SFT 6
629 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
630 #define RT5645_G_RM_R_SM_R_SFT 14
637 #define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
638 #define RT5645_G_OM_R_SM_R_SFT 6
653 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
654 #define RT5645_M_DAC_R1_SPM_L_SFT 14
757 #define RT5645_M_DAC_R1_LM (0x1 << 14)
758 #define RT5645_M_DAC_R1_LM_SFT 14
769 #define RT5645_PWR_I2S2 (0x1 << 14)
770 #define RT5645_PWR_I2S2_BIT 14
783 #define RT5645_PWR_DAC_R2 (0x1 << 6)
784 #define RT5645_PWR_DAC_R2_BIT 6
795 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
796 #define RT5645_PWR_ADC_MF_L_BIT 14
809 #define RT5645_PWR_PDM2 (0x1 << 6)
810 #define RT5645_PWR_PDM2_BIT 6
819 #define RT5645_PWR_FV1 (0x1 << 14)
820 #define RT5645_PWR_FV1_BIT 14
831 #define RT5645_PWR_HP_R (0x1 << 6)
832 #define RT5645_PWR_HP_R_BIT 6
845 #define RT5645_PWR_BST2 (0x1 << 14)
846 #define RT5645_PWR_BST2_BIT 14
871 #define RT5645_PWR_OM_R (0x1 << 14)
872 #define RT5645_PWR_OM_R_BIT 14
885 #define RT5645_PWR_HM_R (0x1 << 6)
886 #define RT5645_PWR_HM_R_BIT 6
893 #define RT5645_PWR_SV_R (0x1 << 14)
894 #define RT5645_PWR_SV_R_BIT 14
939 #define RT5645_I2S2_SDI_MASK (0x1 << 6)
940 #define RT5645_I2S2_SDI_SFT 6
941 #define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
942 #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
997 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
998 #define RT5645_DAC_L_OSR_SFT 14
999 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1000 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1001 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1002 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1019 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1020 #define RT5645_DMIC_2_EN_SFT 14
1021 #define RT5645_DMIC_2_DIS (0x0 << 14)
1022 #define RT5645_DMIC_2_EN (0x1 << 14)
1062 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1063 #define RT5645_SCLK_SRC_SFT 14
1064 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1065 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1066 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1101 #define RT5645_M1_T_MASK (0x1 << 14)
1102 #define RT5645_M1_T_SFT 14
1103 #define RT5645_M1_T_I2S2 (0x0 << 14)
1104 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1199 #define RT5645_RSTN_MASK (0x1 << 6)
1200 #define RT5645_RSTN_SFT 6
1201 #define RT5645_RSTN_DIS (0x0 << 6)
1202 #define RT5645_RSTN_EN (0x1 << 6)
1255 #define RT5645_DIG_DP_MASK (0x1 << 6)
1256 #define RT5645_DIG_DP_SFT 6
1257 #define RT5645_DIG_DP_DIS (0x0 << 6)
1258 #define RT5645_DIG_DP_EN (0x1 << 6)
1277 #define RT5645_CP_FQ_96_KHZ 6
1285 #define RT5645_SPK_AG_MASK (0x1 << 14)
1286 #define RT5645_SPK_AG_SFT 14
1287 #define RT5645_SPK_AG_DIS (0x0 << 14)
1288 #define RT5645_SPK_AG_EN (0x1 << 14)
1295 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1296 #define RT5645_MIC2_BS_SFT 14
1297 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1298 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1320 #define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1321 #define RT5645_MIC2_OVTH_SFT 6
1322 #define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1323 #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1324 #define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1349 #define RT5645_EQ_UPD (0x1 << 14)
1350 #define RT5645_EQ_UPD_BIT 14
1371 #define RT5645_EQ_HPF2_MASK (0x1 << 6)
1372 #define RT5645_EQ_HPF2_SFT 6
1373 #define RT5645_EQ_HPF2_DIS (0x0 << 6)
1374 #define RT5645_EQ_HPF2_EN (0x1 << 6)
1412 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1413 #define RT5645_DRC_AGC_SFT 14
1414 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1415 #define RT5645_DRC_AGC_EN (0x1 << 14)
1452 #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1453 #define RT5645_DRC_AGC_NG_SFT 6
1454 #define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1455 #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1468 #define RT5645_ANC_MASK (0x1 << 14)
1469 #define RT5645_ANC_SFT 14
1470 #define RT5645_ANC_DIS (0x0 << 14)
1471 #define RT5645_ANC_EN (0x1 << 14)
1496 #define RT5645_ANC_SW_MASK (0x1 << 6)
1497 #define RT5645_ANC_SW_SFT 6
1498 #define RT5645_ANC_SW_NOR (0x0 << 6)
1499 #define RT5645_ANC_SW_AUTO (0x1 << 6)
1514 #define RT5645_ANC_CD_MASK (0x1 << 6)
1515 #define RT5645_ANC_CD_SFT 6
1516 #define RT5645_ANC_CD_BOTH (0x0 << 6)
1517 #define RT5645_ANC_CD_IND (0x1 << 6)
1551 #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1552 #define RT5645_JD_SPR_TRG_SFT 6
1553 #define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1554 #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1607 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1608 #define RT5645_IRQ_OT_SFT 14
1609 #define RT5645_IRQ_OT_BP (0x0 << 14)
1610 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1638 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1639 #define RT5645_IRQ_MB2_OC_SFT 14
1640 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1641 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1654 #define RT5645_MB2_OC_P_MASK (0x1 << 6)
1655 #define RT5645_MB2_OC_P_SFT 6
1656 #define RT5645_MB2_OC_P_NOR (0x0 << 6)
1657 #define RT5645_MB2_OC_P_INV (0x1 << 6)
1668 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1669 #define RT5645_GP2_PIN_SFT 14
1670 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1671 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1695 #define RT5645_GP6_PIN_MASK (0x1 << 6)
1696 #define RT5645_GP6_PIN_SFT 6
1697 #define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1698 #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1741 #define RT5645_GP3_P_MASK (0x1 << 6)
1742 #define RT5645_GP3_P_SFT 6
1743 #define RT5645_GP3_P_NOR (0x0 << 6)
1744 #define RT5645_GP3_P_INV (0x1 << 6)
1801 #define RT5645_SEQ1_PT_RUN (0x1 << 6)
1802 #define RT5645_SEQ1_PT_RUN_BIT 6
1827 #define RT5645_SCB_MASK (0x1 << 14)
1828 #define RT5645_SCB_SFT 14
1829 #define RT5645_SCB_DIS (0x0 << 14)
1830 #define RT5645_SCB_EN (0x1 << 14)
1849 #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1850 #define RT5645_M_BB_HPF_R_SFT 6
1858 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1859 #define RT5645_M_MP3_R_SFT 14
1870 #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1871 #define RT5645_M_MP3_ORG_L_SFT 6
1890 #define RT5645_3D_HP_MASK (0x1 << 14)
1891 #define RT5645_3D_HP_SFT 14
1892 #define RT5645_3D_HP_DIS (0x0 << 14)
1893 #define RT5645_3D_HP_EN (0x1 << 14)
1910 #define RT5645_M_3D_REVB_MASK (0x1 << 6)
1911 #define RT5645_M_3D_REVB_SFT 6
1926 #define RT5645_ZD_T_MASK (0x3 << 6)
1927 #define RT5645_ZD_T_SFT 6
1948 #define RT5645_HPD_RCV_MASK (0x7 << 6)
1949 #define RT5645_HPD_RCV_SFT 6
1977 #define RT5645_SPO_SV_MASK (0x1 << 14)
1978 #define RT5645_SPO_SV_SFT 14
1979 #define RT5645_SPO_SV_DIS (0x0 << 14)
1980 #define RT5645_SPO_SV_EN (0x1 << 14)
2002 #define RT5645_M_ZCD_SM_R (0x1 << 6)
2017 #define RT5645_RST_4BTN_IL_MASK (0x1 << 14)
2018 #define RT5645_RST_4BTN_IL_RST (0x0 << 14)
2019 #define RT5645_RST_4BTN_IL_NORM (0x1 << 14)
2023 #define RT5645_DA1_ZDET_SFT 6
2050 #define RT5645_HPF_FC_MASK (0x3f << 6)
2051 #define RT5645_HPF_FC_SFT 6
2064 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2066 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2075 #define RT5645_DP_ATT_MASK (0x3 << 14)
2076 #define RT5645_DP_ATT_SFT 14
2093 #define RT5645_JD_CBJ_POL (0x1 << 6)