Lines Matching +full:11 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
17 /* I/O - Output */
22 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
47 /* Mixer - PDM */
49 /* Mixer - ADC */
54 /* Mixer - DAC */
92 /* Format - ADC/DAC */
99 /* Format - TDM Control */
105 /* Function - Analog */
121 /* Function - Digital */
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
220 #define RT5645_VOL_L_SFT 14
243 #define RT5645_CAPLESS_EN (0x1 << 11)
248 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
307 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
308 #define RT5645_STO1_ADC_L_BST_SFT 14
315 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
316 #define RT5645_MONO_ADC_L_BST_SFT 14
327 #define RT5645_M_ADC_L1 (0x1 << 14)
328 #define RT5645_M_ADC_L1_SFT 14
335 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
336 #define RT5645_ADC_2_SRC_SFT 11
347 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
348 #define RT5645_M_MONO_ADC_L1_SFT 14
355 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
356 #define RT5645_MONO_ADC_L2_SRC_SFT 11
375 #define RT5645_M_DAC1_L (0x1 << 14)
376 #define RT5645_M_DAC1_L_SFT 14
395 #define RT5645_M_DAC_L1 (0x1 << 14)
396 #define RT5645_M_DAC_L1_SFT 14
401 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
402 #define RT5645_DAC_L2_STO_L_VOL_SFT 11
425 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
426 #define RT5645_M_DAC_L1_MONO_L_SFT 14
431 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
432 #define RT5645_DAC_L2_MONO_L_VOL_SFT 11
453 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
454 #define RT5645_STO_L_DAC_L_VOL_SFT 14
459 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
460 #define RT5645_M_STO_R_DAC_R_SFT 11
501 #define RT5645_M_PDM1_L (0x1 << 14)
502 #define RT5645_M_PDM1_L_SFT 14
507 #define RT5645_PDM2_L_MASK (0x1 << 11)
508 #define RT5645_PDM2_L_SFT 11
600 #define RT5645_M_DAC1_HM (0x1 << 14)
601 #define RT5645_M_DAC1_HM_SFT 14
607 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
608 #define RT5645_G_RM_L_SM_L_SFT 14
629 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
630 #define RT5645_G_RM_R_SM_R_SFT 14
653 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
654 #define RT5645_M_DAC_R1_SPM_L_SFT 14
659 #define RT5645_M_BST3_SPM_L (0x1 << 11)
660 #define RT5645_M_BST3_SPM_L_SFT 11
757 #define RT5645_M_DAC_R1_LM (0x1 << 14)
758 #define RT5645_M_DAC_R1_LM_SFT 14
763 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
764 #define RT5645_G_LOUTMIX_SFT 11
769 #define RT5645_PWR_I2S2 (0x1 << 14)
770 #define RT5645_PWR_I2S2_BIT 14
775 #define RT5645_PWR_DAC_R1 (0x1 << 11)
776 #define RT5645_PWR_DAC_R1_BIT 11
795 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
796 #define RT5645_PWR_ADC_MF_L_BIT 14
801 #define RT5645_PWR_DAC_S1F (0x1 << 11)
802 #define RT5645_PWR_DAC_S1F_BIT 11
819 #define RT5645_PWR_FV1 (0x1 << 14)
820 #define RT5645_PWR_FV1_BIT 14
825 #define RT5645_PWR_BG (0x1 << 11)
826 #define RT5645_PWR_BG_BIT 11
845 #define RT5645_PWR_BST2 (0x1 << 14)
846 #define RT5645_PWR_BST2_BIT 14
851 #define RT5645_PWR_MB1 (0x1 << 11)
852 #define RT5645_PWR_MB1_BIT 11
871 #define RT5645_PWR_OM_R (0x1 << 14)
872 #define RT5645_PWR_OM_R_BIT 14
877 #define RT5645_PWR_RM_L (0x1 << 11)
878 #define RT5645_PWR_RM_L_BIT 11
893 #define RT5645_PWR_SV_R (0x1 << 14)
894 #define RT5645_PWR_SV_R_BIT 14
895 #define RT5645_PWR_HV_L (0x1 << 11)
896 #define RT5645_PWR_HV_L_BIT 11
955 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
956 #define RT5645_I2S_BCLK_MS2_SFT 11
957 #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
958 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
997 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
998 #define RT5645_DAC_L_OSR_SFT 14
999 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1000 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1001 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1002 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1009 #define RT5645_DAHPF_EN (0x1 << 11)
1010 #define RT5645_DAHPF_EN_SFT 11
1019 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1020 #define RT5645_DMIC_2_EN_SFT 14
1021 #define RT5645_DMIC_2_DIS (0x0 << 14)
1022 #define RT5645_DMIC_2_EN (0x1 << 14)
1062 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1063 #define RT5645_SCLK_SRC_SFT 14
1064 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1065 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1066 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1067 #define RT5645_PLL1_SRC_MASK (0x7 << 11)
1068 #define RT5645_PLL1_SRC_SFT 11
1069 #define RT5645_PLL1_SRC_MCLK (0x0 << 11)
1070 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1071 #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
1072 #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
1073 #define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
1093 #define RT5645_PLL_M_BP (0x1 << 11)
1094 #define RT5645_PLL_M_BP_SFT 11
1101 #define RT5645_M1_T_MASK (0x1 << 14)
1102 #define RT5645_M1_T_SFT 14
1103 #define RT5645_M1_T_I2S2 (0x0 << 14)
1104 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1173 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1174 #define RT5645_CLSD_OM_SFT 11
1175 #define RT5645_CLSD_OM_MONO (0x0 << 11)
1176 #define RT5645_CLSD_OM_STO (0x1 << 11)
1237 #define RT5645_BPS_MASK (0x1 << 11)
1238 #define RT5645_BPS_SFT 11
1239 #define RT5645_BPS_DIS (0x0 << 11)
1240 #define RT5645_BPS_EN (0x1 << 11)
1285 #define RT5645_SPK_AG_MASK (0x1 << 14)
1286 #define RT5645_SPK_AG_SFT 14
1287 #define RT5645_SPK_AG_DIS (0x0 << 14)
1288 #define RT5645_SPK_AG_EN (0x1 << 14)
1295 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1296 #define RT5645_MIC2_BS_SFT 14
1297 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1298 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1307 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1308 #define RT5645_MIC1_OVCD_SFT 11
1309 #define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1310 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1349 #define RT5645_EQ_UPD (0x1 << 14)
1350 #define RT5645_EQ_UPD_BIT 14
1412 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1413 #define RT5645_DRC_AGC_SFT 14
1414 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1415 #define RT5645_DRC_AGC_EN (0x1 << 14)
1468 #define RT5645_ANC_MASK (0x1 << 14)
1469 #define RT5645_ANC_SFT 14
1470 #define RT5645_ANC_DIS (0x0 << 14)
1471 #define RT5645_ANC_EN (0x1 << 14)
1478 #define RT5645_ANC_SN_MASK (0x1 << 11)
1479 #define RT5645_ANC_SN_SFT 11
1480 #define RT5645_ANC_SN_DIS (0x0 << 11)
1481 #define RT5645_ANC_SN_EN (0x1 << 11)
1531 #define RT5645_JD_HP_MASK (0x1 << 11)
1532 #define RT5645_JD_HP_SFT 11
1533 #define RT5645_JD_HP_DIS (0x0 << 11)
1534 #define RT5645_JD_HP_EN (0x1 << 11)
1607 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1608 #define RT5645_IRQ_OT_SFT 14
1609 #define RT5645_IRQ_OT_BP (0x0 << 14)
1610 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1619 #define RT5645_JD_P_MASK (0x1 << 11)
1620 #define RT5645_JD_P_SFT 11
1621 #define RT5645_JD_P_NOR (0x0 << 11)
1622 #define RT5645_JD_P_INV (0x1 << 11)
1638 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1639 #define RT5645_IRQ_MB2_OC_SFT 14
1640 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1641 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1668 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1669 #define RT5645_GP2_PIN_SFT 14
1670 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1671 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1677 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1678 #define RT5645_GP4_PIN_SFT 11
1679 #define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1680 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1721 #define RT5645_GP4_PF_MASK (0x1 << 11)
1722 #define RT5645_GP4_PF_SFT 11
1723 #define RT5645_GP4_PF_IN (0x0 << 11)
1724 #define RT5645_GP4_PF_OUT (0x1 << 11)
1773 #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1774 #define RT5645_SEQ1_ST_SFT 11
1775 #define RT5645_SEQ1_ST_RUN (0x0 << 11)
1776 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1827 #define RT5645_SCB_MASK (0x1 << 14)
1828 #define RT5645_SCB_SFT 14
1829 #define RT5645_SCB_DIS (0x0 << 14)
1830 #define RT5645_SCB_EN (0x1 << 14)
1858 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1859 #define RT5645_M_MP3_R_SFT 14
1890 #define RT5645_3D_HP_MASK (0x1 << 14)
1891 #define RT5645_3D_HP_SFT 14
1892 #define RT5645_3D_HP_DIS (0x0 << 14)
1893 #define RT5645_3D_HP_EN (0x1 << 14)
1898 #define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1899 #define RT5645_3D_1F_MIX_SFT 11
1920 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1921 #define RT5645_1ST_HPF_SFT 11
1922 #define RT5645_1ST_HPF_DIS (0x0 << 11)
1923 #define RT5645_1ST_HPF_EN (0x1 << 11)
1936 #define RT5645_SI_DAC_MASK (0x1 << 11)
1937 #define RT5645_SI_DAC_SFT 11
1938 #define RT5645_SI_DAC_AUTO (0x0 << 11)
1939 #define RT5645_SI_DAC_TEST (0x1 << 11)
1977 #define RT5645_SPO_SV_MASK (0x1 << 14)
1978 #define RT5645_SPO_SV_SFT 14
1979 #define RT5645_SPO_SV_DIS (0x0 << 14)
1980 #define RT5645_SPO_SV_EN (0x1 << 14)
1989 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1990 #define RT5645_ZCD_DIG_SFT 11
1991 #define RT5645_ZCD_DIG_DIS (0x0 << 11)
1992 #define RT5645_ZCD_DIG_EN (0x1 << 11)
2017 #define RT5645_RST_4BTN_IL_MASK (0x1 << 14)
2018 #define RT5645_RST_4BTN_IL_RST (0x0 << 14)
2019 #define RT5645_RST_4BTN_IL_NORM (0x1 << 14)
2064 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2066 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2075 #define RT5645_DP_ATT_MASK (0x3 << 14)
2076 #define RT5645_DP_ATT_SFT 14
2110 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2111 #define RT5645_IF1_ADC1_IN2_SFT 11
2134 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)