Lines Matching +full:6 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5640.h>
22 /* I/O - Output */
27 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
78 /* Format - ADC/DAC */
84 /* Function - Analog */
102 /* Function - Digital */
185 #define RT5640_VOL_L_MUTE (0x1 << 14)
186 #define RT5640_VOL_L_SFT 14
189 #define RT5640_VOL_R_MUTE (0x1 << 6)
190 #define RT5640_VOL_R_SFT 6
209 #define RT5640_IN_DF2 (0x1 << 6)
210 #define RT5640_IN_SFT2 6
257 #define RT5640_ADC_L_BST_MASK (0x3 << 14)
258 #define RT5640_ADC_L_BST_SFT 14
265 #define RT5640_M_ADC_L1 (0x1 << 14)
266 #define RT5640_M_ADC_L1_SFT 14
278 #define RT5640_M_ADC_R1 (0x1 << 6)
279 #define RT5640_M_ADC_R1_SFT 6
284 #define RT5640_M_MONO_ADC_L1 (0x1 << 14)
285 #define RT5640_M_MONO_ADC_L1_SFT 14
297 #define RT5640_M_MONO_ADC_R1 (0x1 << 6)
298 #define RT5640_M_MONO_ADC_R1_SFT 6
314 #define RT5640_M_IF1_DAC_L (0x1 << 14)
315 #define RT5640_M_IF1_DAC_L_SFT 14
318 #define RT5640_M_IF1_DAC_R (0x1 << 6)
319 #define RT5640_M_IF1_DAC_R_SFT 6
322 #define RT5640_M_DAC_L1 (0x1 << 14)
323 #define RT5640_M_DAC_L1_SFT 14
332 #define RT5640_M_DAC_R1 (0x1 << 6)
333 #define RT5640_M_DAC_R1_SFT 6
344 #define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
345 #define RT5640_M_DAC_L1_MONO_L_SFT 14
356 #define RT5640_M_DAC_R1_MONO_R (0x1 << 6)
357 #define RT5640_M_DAC_R1_MONO_R_SFT 6
372 #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
373 #define RT5640_STO_L_DAC_L_VOL_SFT 14
392 #define RT5640_TXDP_SRC_MASK (0x1 << 14)
393 #define RT5640_TXDP_SRC_SFT 14
394 #define RT5640_TXDP_SRC_NOR (0x0 << 14)
395 #define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
398 #define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
399 #define RT5640_DAC_L2_SEL_SFT 14
400 #define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
401 #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
402 #define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
403 #define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
423 #define RT5640_RXDP_SEL_MASK (0x3 << 6)
424 #define RT5640_RXDP_SEL_SFT 6
425 #define RT5640_RXDP_SEL_NOR (0x0 << 6)
426 #define RT5640_RXDP_SEL_L2R (0x1 << 6)
427 #define RT5640_RXDP_SEL_R2L (0x2 << 6)
428 #define RT5640_RXDP_SEL_SWAP (0x3 << 6)
443 #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
444 #define RT5640_IF1_DAC_SEL_SFT 14
445 #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
446 #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
447 #define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
448 #define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
467 #define RT5640_IF3_DAC_SEL_MASK (0x3 << 6)
468 #define RT5640_IF3_DAC_SEL_SFT 6
469 #define RT5640_IF3_DAC_SEL_NOR (0x0 << 6)
470 #define RT5640_IF3_DAC_SEL_SWAP (0x1 << 6)
471 #define RT5640_IF3_DAC_SEL_L2R (0x2 << 6)
472 #define RT5640_IF3_DAC_SEL_R2L (0x3 << 6)
497 #define RT5640_M_HP_L_RM_L (0x1 << 6)
498 #define RT5640_M_HP_L_RM_L_SFT 6
529 #define RT5640_M_HP_R_RM_R (0x1 << 6)
530 #define RT5640_M_HP_R_RM_R_SFT 6
547 #define RT5640_M_DAC1_HM (0x1 << 14)
548 #define RT5640_M_DAC1_HM_SFT 14
555 #define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
556 #define RT5640_G_RM_L_SM_L_SFT 14
563 #define RT5640_G_OM_L_SM_L_MASK (0x3 << 6)
564 #define RT5640_G_OM_L_SM_L_SFT 6
577 #define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
578 #define RT5640_G_RM_R_SM_R_SFT 14
585 #define RT5640_G_OM_R_SM_R_MASK (0x3 << 6)
586 #define RT5640_G_OM_R_SM_R_SFT 6
601 #define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
602 #define RT5640_M_DAC_L1_SPM_L_SFT 14
625 #define RT5640_M_DAC_L2_MM (0x1 << 14)
626 #define RT5640_M_DAC_L2_MM_SFT 14
661 #define RT5640_M_BST2_OM_L (0x1 << 6)
662 #define RT5640_M_BST2_OM_L_SFT 6
701 #define RT5640_M_BST2_OM_R (0x1 << 6)
702 #define RT5640_M_BST2_OM_R_SFT 6
719 #define RT5640_M_DAC_R1_LM (0x1 << 14)
720 #define RT5640_M_DAC_R1_LM_SFT 14
731 #define RT5640_PWR_I2S2 (0x1 << 14)
732 #define RT5640_PWR_I2S2_BIT 14
739 #define RT5640_PWR_DAC_R2 (0x1 << 6)
740 #define RT5640_PWR_DAC_R2_BIT 6
751 #define RT5640_PWR_ADC_MF_L (0x1 << 14)
752 #define RT5640_PWR_ADC_MF_L_BIT 14
761 #define RT5640_PWR_FV1 (0x1 << 14)
762 #define RT5640_PWR_FV1_BIT 14
775 #define RT5640_PWR_HP_R (0x1 << 6)
776 #define RT5640_PWR_HP_R_BIT 6
789 #define RT5640_PWR_BST2 (0x1 << 14)
790 #define RT5640_PWR_BST2_BIT 14
803 #define RT5640_PWR_OM_R (0x1 << 14)
804 #define RT5640_PWR_OM_R_BIT 14
817 #define RT5640_PWR_SV_R (0x1 << 14)
818 #define RT5640_PWR_SV_R_BIT 14
867 #define RT5640_I2S2_SDI_MASK (0x1 << 6)
868 #define RT5640_I2S2_SDI_SFT 6
869 #define RT5640_I2S2_SDI_I2S1 (0x0 << 6)
870 #define RT5640_I2S2_SDI_I2S2 (0x1 << 6)
929 #define RT5640_DAC_L_OSR_MASK (0x3 << 14)
930 #define RT5640_DAC_L_OSR_SFT 14
931 #define RT5640_DAC_L_OSR_128 (0x0 << 14)
932 #define RT5640_DAC_L_OSR_64 (0x1 << 14)
933 #define RT5640_DAC_L_OSR_32 (0x2 << 14)
934 #define RT5640_DAC_L_OSR_16 (0x3 << 14)
951 #define RT5640_DMIC_2_EN_MASK (0x1 << 14)
952 #define RT5640_DMIC_2_EN_SFT 14
953 #define RT5640_DMIC_2_DIS (0x0 << 14)
954 #define RT5640_DMIC_2_EN (0x1 << 14)
983 #define RT5640_SCLK_SRC_MASK (0x3 << 14)
984 #define RT5640_SCLK_SRC_SFT 14
985 #define RT5640_SCLK_SRC_MCLK (0x0 << 14)
986 #define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
987 #define RT5640_SCLK_SRC_RCCLK (0x2 << 14)
1021 #define RT5640_M1_T_MASK (0x1 << 14)
1022 #define RT5640_M1_T_SFT 14
1023 #define RT5640_M1_T_I2S2 (0x0 << 14)
1024 #define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1047 #define RT5640_MDA_R_M_MASK (0x1 << 14)
1048 #define RT5640_MDA_R_M_SFT 14
1049 #define RT5640_MDA_R_M_NOR (0x0 << 14)
1050 #define RT5640_MDA_R_M_ASYN (0x1 << 14)
1146 #define RT5640_RSTN_MASK (0x1 << 6)
1147 #define RT5640_RSTN_SFT 6
1148 #define RT5640_RSTN_DIS (0x0 << 6)
1149 #define RT5640_RSTN_EN (0x1 << 6)
1202 #define RT5640_DIG_DP_MASK (0x1 << 6)
1203 #define RT5640_DIG_DP_SFT 6
1204 #define RT5640_DIG_DP_DIS (0x0 << 6)
1205 #define RT5640_DIG_DP_EN (0x1 << 6)
1224 #define RT5640_CP_FQ_96_KHZ 6
1241 #define RT5640_IB_HP_MASK (0x3 << 6)
1242 #define RT5640_IB_HP_SFT 6
1243 #define RT5640_IB_HP_125IL (0x0 << 6)
1244 #define RT5640_IB_HP_25IL (0x1 << 6)
1245 #define RT5640_IB_HP_5IL (0x2 << 6)
1246 #define RT5640_IB_HP_1IL (0x3 << 6)
1253 #define RT5640_SPK_AG_MASK (0x1 << 14)
1254 #define RT5640_SPK_AG_SFT 14
1255 #define RT5640_SPK_AG_DIS (0x0 << 14)
1256 #define RT5640_SPK_AG_EN (0x1 << 14)
1263 #define RT5640_MIC2_BS_MASK (0x1 << 14)
1264 #define RT5640_MIC2_BS_SFT 14
1265 #define RT5640_MIC2_BS_9AV (0x0 << 14)
1266 #define RT5640_MIC2_BS_75AV (0x1 << 14)
1288 #define RT5640_MIC2_OVTH_MASK (0x3 << 6)
1289 #define RT5640_MIC2_OVTH_SFT 6
1290 #define RT5640_MIC2_OVTH_600UA (0x0 << 6)
1291 #define RT5640_MIC2_OVTH_1500UA (0x1 << 6)
1292 #define RT5640_MIC2_OVTH_2000UA (0x2 << 6)
1307 #define RT5640_EQ_UPD (0x1 << 14)
1308 #define RT5640_EQ_UPD_BIT 14
1329 #define RT5640_EQ_HPF2_MASK (0x1 << 6)
1330 #define RT5640_EQ_HPF2_SFT 6
1331 #define RT5640_EQ_HPF2_DIS (0x0 << 6)
1332 #define RT5640_EQ_HPF2_EN (0x1 << 6)
1369 #define RT5640_DRC_AGC_MASK (0x1 << 14)
1370 #define RT5640_DRC_AGC_SFT 14
1371 #define RT5640_DRC_AGC_DIS (0x0 << 14)
1372 #define RT5640_DRC_AGC_EN (0x1 << 14)
1409 #define RT5640_DRC_AGC_NG_MASK (0x1 << 6)
1410 #define RT5640_DRC_AGC_NG_SFT 6
1411 #define RT5640_DRC_AGC_NG_DIS (0x0 << 6)
1412 #define RT5640_DRC_AGC_NG_EN (0x1 << 6)
1425 #define RT5640_ANC_MASK (0x1 << 14)
1426 #define RT5640_ANC_SFT 14
1427 #define RT5640_ANC_DIS (0x0 << 14)
1428 #define RT5640_ANC_EN (0x1 << 14)
1453 #define RT5640_ANC_SW_MASK (0x1 << 6)
1454 #define RT5640_ANC_SW_SFT 6
1455 #define RT5640_ANC_SW_NOR (0x0 << 6)
1456 #define RT5640_ANC_SW_AUTO (0x1 << 6)
1471 #define RT5640_ANC_CD_MASK (0x1 << 6)
1472 #define RT5640_ANC_CD_SFT 6
1473 #define RT5640_ANC_CD_BOTH (0x0 << 6)
1474 #define RT5640_ANC_CD_IND (0x1 << 6)
1508 #define RT5640_JD_SPR_TRG_MASK (0x1 << 6)
1509 #define RT5640_JD_SPR_TRG_SFT 6
1510 #define RT5640_JD_SPR_TRG_LO (0x0 << 6)
1511 #define RT5640_JD_SPR_TRG_HI (0x1 << 6)
1564 #define RT5640_IRQ_OT_MASK (0x1 << 14)
1565 #define RT5640_IRQ_OT_SFT 14
1566 #define RT5640_IRQ_OT_BP (0x0 << 14)
1567 #define RT5640_IRQ_OT_NOR (0x1 << 14)
1590 #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1591 #define RT5640_IRQ_MB2_OC_SFT 14
1592 #define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
1593 #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1606 #define RT5640_MB2_OC_P_MASK (0x1 << 6)
1607 #define RT5640_MB2_OC_P_SFT 6
1608 #define RT5640_MB2_OC_P_NOR (0x0 << 6)
1609 #define RT5640_MB2_OC_P_INV (0x1 << 6)
1627 #define RT5640_GP2_PIN_MASK (0x1 << 14)
1628 #define RT5640_GP2_PIN_SFT 14
1629 #define RT5640_GP2_PIN_GPIO2 (0x0 << 14)
1630 #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1670 #define RT5640_GP3_P_MASK (0x1 << 6)
1671 #define RT5640_GP3_P_SFT 6
1672 #define RT5640_GP3_P_NOR (0x0 << 6)
1673 #define RT5640_GP3_P_INV (0x1 << 6)
1699 /* FM34-500 Register Control 1 (0xc4) */
1702 /* FM34-500 Register Control 2 (0xc5) */
1705 /* FM34-500 Register Control 3 (0xc6) */
1708 #define RT5640_DSP_DS_MASK (0x1 << 14)
1709 #define RT5640_DSP_DS_SFT 14
1710 #define RT5640_DSP_DS_FM3010 (0x1 << 14)
1711 #define RT5640_DSP_DS_TEMP (0x1 << 14)
1768 #define RT5640_SEQ1_PT_RUN (0x1 << 6)
1769 #define RT5640_SEQ1_PT_RUN_BIT 6
1794 #define RT5640_SCB_MASK (0x1 << 14)
1795 #define RT5640_SCB_SFT 14
1796 #define RT5640_SCB_DIS (0x0 << 14)
1797 #define RT5640_SCB_EN (0x1 << 14)
1816 #define RT5640_M_BB_HPF_R_MASK (0x1 << 6)
1817 #define RT5640_M_BB_HPF_R_SFT 6
1824 #define RT5640_M_MP3_R_MASK (0x1 << 14)
1825 #define RT5640_M_MP3_R_SFT 14
1836 #define RT5640_M_MP3_ORG_L_MASK (0x1 << 6)
1837 #define RT5640_M_MP3_ORG_L_SFT 6
1856 #define RT5640_3D_HP_MASK (0x1 << 14)
1857 #define RT5640_3D_HP_SFT 14
1858 #define RT5640_3D_HP_DIS (0x0 << 14)
1859 #define RT5640_3D_HP_EN (0x1 << 14)
1876 #define RT5640_M_3D_REVB_MASK (0x1 << 6)
1877 #define RT5640_M_3D_REVB_SFT 6
1892 #define RT5640_ZD_T_MASK (0x3 << 6)
1893 #define RT5640_ZD_T_SFT 6
1914 #define RT5640_HPD_RCV_MASK (0x7 << 6)
1915 #define RT5640_HPD_RCV_SFT 6
1943 #define RT5640_SPO_SV_MASK (0x1 << 14)
1944 #define RT5640_SPO_SV_SFT 14
1945 #define RT5640_SPO_SV_DIS (0x0 << 14)
1946 #define RT5640_SPO_SV_EN (0x1 << 14)
1968 #define RT5640_M_ZCD_SM_R (0x1 << 6)
1981 #define RT5640_EN_LOUT_DF (0x1 << 14)
1982 #define RT5640_EN_LOUT_DF_SFT 14
2038 #define RT5640_HPF_FC_MASK (0x3f << 6)
2039 #define RT5640_HPF_FC_SFT 6
2052 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2054 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2063 #define RT5640_DP_ATT_MASK (0x3 << 14)
2064 #define RT5640_DP_ATT_SFT 14