Lines Matching +full:1 +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-only */
21 #define PCM512x_RESET (PCM512x_PAGE_BASE(0) + 1)
24 #define PCM512x_PLL_EN (PCM512x_PAGE_BASE(0) + 4)
81 #define PCM512x_OUTPUT_AMPLITUDE (PCM512x_PAGE_BASE(1) + 1)
82 #define PCM512x_ANALOG_GAIN_CTRL (PCM512x_PAGE_BASE(1) + 2)
83 #define PCM512x_UNDERVOLTAGE_PROT (PCM512x_PAGE_BASE(1) + 5)
84 #define PCM512x_ANALOG_MUTE_CTRL (PCM512x_PAGE_BASE(1) + 6)
85 #define PCM512x_ANALOG_GAIN_BOOST (PCM512x_PAGE_BASE(1) + 7)
86 #define PCM512x_VCOM_CTRL_1 (PCM512x_PAGE_BASE(1) + 8)
87 #define PCM512x_VCOM_CTRL_2 (PCM512x_PAGE_BASE(1) + 9)
89 #define PCM512x_CRAM_CTRL (PCM512x_PAGE_BASE(44) + 1)
96 /* Page 0, Register 1 - reset */
97 #define PCM512x_RSTR (1 << 0)
98 #define PCM512x_RSTM (1 << 4)
100 /* Page 0, Register 2 - power */
101 #define PCM512x_RQPD (1 << 0)
103 #define PCM512x_RQST (1 << 4)
104 #define PCM512x_RQST_SHIFT 4
106 /* Page 0, Register 3 - mute */
107 #define PCM512x_RQMR (1 << 0)
109 #define PCM512x_RQML (1 << 4)
110 #define PCM512x_RQML_SHIFT 4
112 /* Page 0, Register 4 - PLL */
113 #define PCM512x_PLLE (1 << 0)
115 #define PCM512x_PLCK (1 << 4)
116 #define PCM512x_PLCK_SHIFT 4
118 /* Page 0, Register 7 - DSP */
119 #define PCM512x_SDSL (1 << 0)
121 #define PCM512x_DEMP (1 << 4)
122 #define PCM512x_DEMP_SHIFT 4
124 /* Page 0, Register 8 - GPIO output enable */
125 #define PCM512x_G1OE (1 << 0)
126 #define PCM512x_G2OE (1 << 1)
127 #define PCM512x_G3OE (1 << 2)
128 #define PCM512x_G4OE (1 << 3)
129 #define PCM512x_G5OE (1 << 4)
130 #define PCM512x_G6OE (1 << 5)
132 /* Page 0, Register 9 - BCK, LRCLK configuration */
133 #define PCM512x_LRKO (1 << 0)
135 #define PCM512x_BCKO (1 << 4)
136 #define PCM512x_BCKO_SHIFT 4
137 #define PCM512x_BCKP (1 << 5)
140 /* Page 0, Register 12 - Master mode BCK, LRCLK reset */
141 #define PCM512x_RLRK (1 << 0)
143 #define PCM512x_RBCK (1 << 1)
144 #define PCM512x_RBCK_SHIFT 1
146 /* Page 0, Register 13 - PLL reference */
147 #define PCM512x_SREF (7 << 4)
148 #define PCM512x_SREF_SHIFT 4
149 #define PCM512x_SREF_SCK (0 << 4)
150 #define PCM512x_SREF_BCK (1 << 4)
151 #define PCM512x_SREF_GPIO (3 << 4)
153 /* Page 0, Register 14 - DAC reference */
154 #define PCM512x_SDAC (7 << 4)
155 #define PCM512x_SDAC_SHIFT 4
156 #define PCM512x_SDAC_MCK (0 << 4)
157 #define PCM512x_SDAC_PLL (1 << 4)
158 #define PCM512x_SDAC_SCK (3 << 4)
159 #define PCM512x_SDAC_BCK (4 << 4)
160 #define PCM512x_SDAC_GPIO (5 << 4)
162 /* Page 0, Register 16, 18 - GPIO source for DAC, PLL */
166 #define PCM512x_GREF_GPIO2 (1 << 0)
169 #define PCM512x_GREF_GPIO5 (4 << 0)
172 /* Page 0, Register 19 - synchronize */
173 #define PCM512x_RQSY (1 << 0)
175 #define PCM512x_RQSY_HALT (1 << 0)
177 /* Page 0, Register 34 - fs speed mode */
181 #define PCM512x_FSSP_96KHZ (1 << 0)
185 /* Page 0, Register 37 - Error detection */
186 #define PCM512x_IPLK (1 << 0)
187 #define PCM512x_DCAS (1 << 1)
188 #define PCM512x_IDCM (1 << 2)
189 #define PCM512x_IDCH (1 << 3)
190 #define PCM512x_IDSK (1 << 4)
191 #define PCM512x_IDBK (1 << 5)
192 #define PCM512x_IDFS (1 << 6)
194 /* Page 0, Register 40 - I2S configuration */
198 #define PCM512x_ALEN_20 (1 << 0)
201 #define PCM512x_AFMT (3 << 4)
202 #define PCM512x_AFMT_SHIFT 4
203 #define PCM512x_AFMT_I2S (0 << 4)
204 #define PCM512x_AFMT_DSP (1 << 4)
205 #define PCM512x_AFMT_RTJ (2 << 4)
206 #define PCM512x_AFMT_LTJ (3 << 4)
208 /* Page 0, Register 42 - DAC routing */
210 #define PCM512x_AUPL_SHIFT 4
212 /* Page 0, Register 59 - auto mute */
214 #define PCM512x_ATML_SHIFT 4
216 /* Page 0, Register 63 - ramp rates */
218 #define PCM512x_VNDS_SHIFT 4
222 /* Page 0, Register 64 - emergency ramp rates */
224 #define PCM512x_VEDS_SHIFT 4
226 /* Page 0, Register 65 - Digital mute enables */
228 #define PCM512x_AMLE_SHIFT 1
231 /* Page 0, Register 80-85, GPIO output selection */
235 #define PCM512x_GxSL_DSP (1 << 0)
238 #define PCM512x_GxSL_AMUTL (4 << 0)
250 /* Page 1, Register 2 - analog volume control */
252 #define PCM512x_LAGN_SHIFT 4
254 /* Page 1, Register 7 - analog boost control */
256 #define PCM512x_AGBL_SHIFT 4