Lines Matching +full:ch3 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
38 { 1, 0x0 },
39 { 2, 0x2 },
40 { 4, 0x3 },
41 { 8, 0x4 },
42 { 16, 0x5 },
43 { 32, 0x6 },
44 { 3, 0x7 },
45 { 6, 0xa },
46 { 12, 0xb },
47 { 24, 0xc },
52 { 512000, 0x01 },
53 { 256000, 0x02 },
54 { 128000, 0x04 },
55 { 64000, 0x08 },
56 { 32000, 0x10 },
57 { 8000, 0x20 },
58 { 4000, 0x40 },
62 { 1, 0x0 },
63 { 2, 0x1 },
64 { 4, 0x2 },
65 { 8, 0x3 },
73 { 256, 0 }, /* OSR 256, SRC 1 */
77 {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
78 {NAU8540_REG_CLOCK_CTRL, 0x0000},
79 {NAU8540_REG_CLOCK_SRC, 0x0000},
80 {NAU8540_REG_FLL1, 0x0001},
81 {NAU8540_REG_FLL2, 0x3126},
82 {NAU8540_REG_FLL3, 0x0008},
83 {NAU8540_REG_FLL4, 0x0010},
84 {NAU8540_REG_FLL5, 0xC000},
85 {NAU8540_REG_FLL6, 0x6000},
86 {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
87 {NAU8540_REG_PCM_CTRL0, 0x000B},
88 {NAU8540_REG_PCM_CTRL1, 0x3010},
89 {NAU8540_REG_PCM_CTRL2, 0x0800},
90 {NAU8540_REG_PCM_CTRL3, 0x0000},
91 {NAU8540_REG_PCM_CTRL4, 0x000F},
92 {NAU8540_REG_ALC_CONTROL_1, 0x0000},
93 {NAU8540_REG_ALC_CONTROL_2, 0x700B},
94 {NAU8540_REG_ALC_CONTROL_3, 0x0022},
95 {NAU8540_REG_ALC_CONTROL_4, 0x1010},
96 {NAU8540_REG_ALC_CONTROL_5, 0x1010},
97 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
98 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
99 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
100 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
101 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
102 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
103 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
104 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
105 {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
106 {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
107 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
108 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
109 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
110 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
111 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
112 {NAU8540_REG_DIGITAL_MUX, 0x00E4},
113 {NAU8540_REG_GPIO_CTRL, 0x0000},
114 {NAU8540_REG_MISC_CTRL, 0x0000},
115 {NAU8540_REG_I2C_CTRL, 0xEFFF},
116 {NAU8540_REG_VMID_CTRL, 0x0000},
117 {NAU8540_REG_MUTE, 0x0000},
118 {NAU8540_REG_ANALOG_ADC1, 0x0011},
119 {NAU8540_REG_ANALOG_ADC2, 0x0020},
120 {NAU8540_REG_ANALOG_PWR, 0x0000},
121 {NAU8540_REG_MIC_BIAS, 0x0004},
122 {NAU8540_REG_REFERENCE, 0x0000},
123 {NAU8540_REG_FEPGA1, 0x0000},
124 {NAU8540_REG_FEPGA2, 0x0000},
125 {NAU8540_REG_FEPGA3, 0x0101},
126 {NAU8540_REG_FEPGA4, 0x0101},
127 {NAU8540_REG_PWR, 0x0000},
182 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
183 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
187 0, 0x520, 0, adc_vol_tlv),
189 0, 0x520, 0, adc_vol_tlv),
191 0, 0x520, 0, adc_vol_tlv),
193 0, 0x520, 0, adc_vol_tlv),
196 0, 0x25, 0, fepga_gain_tlv),
198 8, 0x25, 0, fepga_gain_tlv),
200 0, 0x25, 0, fepga_gain_tlv),
202 8, 0x25, 0, fepga_gain_tlv),
218 SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
227 digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in nau8540_fepga_event()
240 regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2, in nau8540_fepga_event()
250 return 0; in nau8540_fepga_event()
256 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in nau8540_precharge_event()
261 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE, in nau8540_precharge_event()
264 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE, in nau8540_precharge_event()
265 NAU8540_DISCHRG_EN, 0); in nau8540_precharge_event()
266 regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2, in nau8540_precharge_event()
267 NAU8540_ACDC_CTL_MASK, 0); in nau8540_precharge_event()
272 return 0; in nau8540_precharge_event()
278 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in adc_power_control()
284 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT, in adc_power_control()
286 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
287 NAU8540_I2S_DO12_TRI, 0); in adc_power_control()
288 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
289 NAU8540_I2S_DO34_TRI, 0); in adc_power_control()
291 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
293 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
295 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT, in adc_power_control()
296 NAU8540_ADC_ALL_EN, 0); in adc_power_control()
298 return 0; in adc_power_control()
304 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in aiftx_power_control()
308 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); in aiftx_power_control()
309 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); in aiftx_power_control()
311 return 0; in aiftx_power_control()
315 SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
316 SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
323 SND_SOC_DAPM_PGA_S("Frontend PGA1", 0, NAU8540_REG_PWR, 12, 0,
325 SND_SOC_DAPM_PGA_S("Frontend PGA2", 0, NAU8540_REG_PWR, 13, 0,
327 SND_SOC_DAPM_PGA_S("Frontend PGA3", 0, NAU8540_REG_PWR, 14, 0,
329 SND_SOC_DAPM_PGA_S("Frontend PGA4", 0, NAU8540_REG_PWR, 15, 0,
332 SND_SOC_DAPM_PGA_S("Precharge", 1, SND_SOC_NOPM, 0, 0,
335 SND_SOC_DAPM_PGA_S("ADC CH1", 2, NAU8540_REG_ANALOG_PWR, 0, 0,
337 SND_SOC_DAPM_PGA_S("ADC CH2", 2, NAU8540_REG_ANALOG_PWR, 1, 0,
339 SND_SOC_DAPM_PGA_S("ADC CH3", 2, NAU8540_REG_ANALOG_PWR, 2, 0,
341 SND_SOC_DAPM_PGA_S("ADC CH4", 2, NAU8540_REG_ANALOG_PWR, 3, 0,
345 SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
346 SND_SOC_DAPM_MUX("Digital CH3 Mux",
347 SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
349 SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
351 SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
353 SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
370 {"ADC CH3", NULL, "Precharge"},
375 {"ADC CH3", NULL, "MICBIAS2"},
380 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
385 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
388 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
389 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
390 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
391 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
395 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
400 {"AIFTX", NULL, "Digital CH3 Mux"},
409 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); in nau8540_get_osr()
419 struct snd_soc_component *component = dai->component; in nau8540_dai_startup()
424 if (!osr || !osr->osr) in nau8540_dai_startup()
425 return -EINVAL; in nau8540_dai_startup()
427 return snd_pcm_hw_constraint_minmax(substream->runtime, in nau8540_dai_startup()
429 0, CLK_ADC_MAX / osr->osr); in nau8540_dai_startup()
435 struct snd_soc_component *component = dai->component; in nau8540_hw_params()
437 unsigned int val_len = 0; in nau8540_hw_params()
447 if (!osr || !osr->osr) in nau8540_hw_params()
448 return -EINVAL; in nau8540_hw_params()
449 if (params_rate(params) * osr->osr > CLK_ADC_MAX) in nau8540_hw_params()
450 return -EINVAL; in nau8540_hw_params()
451 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_hw_params()
453 osr->clk_src << NAU8540_CLK_ADC_SRC_SFT); in nau8540_hw_params()
469 return -EINVAL; in nau8540_hw_params()
472 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_hw_params()
475 return 0; in nau8540_hw_params()
480 struct snd_soc_component *component = dai->component; in nau8540_set_fmt()
482 unsigned int ctrl1_val = 0, ctrl2_val = 0; in nau8540_set_fmt()
491 return -EINVAL; in nau8540_set_fmt()
501 return -EINVAL; in nau8540_set_fmt()
522 return -EINVAL; in nau8540_set_fmt()
525 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_set_fmt()
528 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_fmt()
530 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_fmt()
531 NAU8540_I2S_DO34_OE, 0); in nau8540_set_fmt()
533 return 0; in nau8540_set_fmt()
537 * nau8540_set_tdm_slot - configure DAI TX TDM.
540 * 0xf for normal 4 channel TDM.
541 * 0xf0 for shifted 4 channel TDM
551 struct snd_soc_component *component = dai->component; in nau8540_set_tdm_slot()
553 unsigned int ctrl2_val = 0, ctrl4_val = 0; in nau8540_set_tdm_slot()
555 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf))) in nau8540_set_tdm_slot()
556 return -EINVAL; in nau8540_set_tdm_slot()
559 if (tx_mask & 0xf0) { in nau8540_set_tdm_slot()
565 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, in nau8540_set_tdm_slot()
568 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_tdm_slot()
570 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_tdm_slot()
574 return 0; in nau8540_set_tdm_slot()
580 struct snd_soc_component *component = dai->component; in nau8540_dai_trigger()
582 struct regmap *regmap = nau8540->regmap; in nau8540_dai_trigger()
584 int ret = 0; in nau8540_dai_trigger()
598 dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val); in nau8540_dai_trigger()
603 NAU8540_PGA_CH_ALL_MUTE, 0); in nau8540_dai_trigger()
604 regmap_write(regmap, NAU8540_REG_RST, 0x1); in nau8540_dai_trigger()
605 regmap_write(regmap, NAU8540_REG_RST, 0); in nau8540_dai_trigger()
607 dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val); in nau8540_dai_trigger()
609 dev_err(nau8540->dev, "Channel recovery failed!!"); in nau8540_dai_trigger()
610 ret = -EIO; in nau8540_dai_trigger()
614 NAU8540_CLK_AGC_EN, 0); in nau8540_dai_trigger()
616 NAU8540_ALC_CH_ALL_EN, 0); in nau8540_dai_trigger()
639 .name = "nau8540-hifi",
651 * nau8540_calc_fll_param - Calculate FLL parameters.
658 * Returns 0 for success or negative error code.
667 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. in nau8540_calc_fll_param()
670 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { in nau8540_calc_fll_param()
676 return -EINVAL; in nau8540_calc_fll_param()
677 fll_param->clk_ref_div = fll_pre_scalar[i].val; in nau8540_calc_fll_param()
680 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { in nau8540_calc_fll_param()
685 return -EINVAL; in nau8540_calc_fll_param()
686 fll_param->ratio = fll_ratio[i].val; in nau8540_calc_fll_param()
689 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be in nau8540_calc_fll_param()
693 fvco_max = 0; in nau8540_calc_fll_param()
695 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { in nau8540_calc_fll_param()
704 return -EINVAL; in nau8540_calc_fll_param()
705 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; in nau8540_calc_fll_param()
707 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional in nau8540_calc_fll_param()
710 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); in nau8540_calc_fll_param()
711 fll_param->fll_int = (fvco >> 16) & 0x3FF; in nau8540_calc_fll_param()
712 fll_param->fll_frac = fvco & 0xFFFF; in nau8540_calc_fll_param()
713 return 0; in nau8540_calc_fll_param()
721 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); in nau8540_fll_apply()
724 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); in nau8540_fll_apply()
725 /* FLL 16-bit fractional input */ in nau8540_fll_apply()
726 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); in nau8540_fll_apply()
727 /* FLL 10-bit integer input */ in nau8540_fll_apply()
729 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); in nau8540_fll_apply()
730 /* FLL pre-scaler */ in nau8540_fll_apply()
733 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); in nau8540_fll_apply()
737 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0); in nau8540_fll_apply()
738 if (fll_param->fll_frac) { in nau8540_fll_apply()
752 NAU8540_SDM_EN | NAU8540_CUTOFF500, 0); in nau8540_fll_apply()
766 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
768 NAU8540_FLL_CLK_SRC_MCLK | 0); in nau8540_set_pll()
772 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
775 (0xf << NAU8540_GAIN_ERR_SFT)); in nau8540_set_pll()
779 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
782 (0xf << NAU8540_GAIN_ERR_SFT)); in nau8540_set_pll()
786 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); in nau8540_set_pll()
787 return -EINVAL; in nau8540_set_pll()
789 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_pll()
794 if (ret < 0) { in nau8540_set_pll()
795 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); in nau8540_set_pll()
798 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", in nau8540_set_pll()
802 nau8540_fll_apply(nau8540->regmap, &fll_param); in nau8540_set_pll()
804 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_pll()
807 return 0; in nau8540_set_pll()
818 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
820 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
821 NAU8540_DCO_EN, 0); in nau8540_set_sysclk()
825 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
827 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
832 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); in nau8540_set_sysclk()
833 return -EINVAL; in nau8540_set_sysclk()
836 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_sysclk()
839 return 0; in nau8540_set_sysclk()
844 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); in nau8540_reset_chip()
845 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); in nau8540_reset_chip()
850 struct regmap *regmap = nau8540->regmap; in nau8540_init_regs()
855 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT)); in nau8540_init_regs()
889 regcache_cache_only(nau8540->regmap, true); in nau8540_suspend()
890 regcache_mark_dirty(nau8540->regmap); in nau8540_suspend()
892 return 0; in nau8540_suspend()
899 regcache_cache_only(nau8540->regmap, false); in nau8540_resume()
900 regcache_sync(nau8540->regmap); in nau8540_resume()
902 return 0; in nau8540_resume()
938 struct device *dev = &i2c->dev; in nau8540_i2c_probe()
945 return -ENOMEM; in nau8540_i2c_probe()
949 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); in nau8540_i2c_probe()
950 if (IS_ERR(nau8540->regmap)) in nau8540_i2c_probe()
951 return PTR_ERR(nau8540->regmap); in nau8540_i2c_probe()
952 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); in nau8540_i2c_probe()
953 if (ret < 0) { in nau8540_i2c_probe()
959 nau8540->dev = dev; in nau8540_i2c_probe()
960 nau8540_reset_chip(nau8540->regmap); in nau8540_i2c_probe()