Lines Matching +full:3 +full:x3
267 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
269 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
436 #define RG_EINT0CEN_SFT 3
438 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
515 #define ACCDET_DSN_CBS_MASK 0x3
516 #define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
520 #define ACCDET_DSN_BIX_MASK 0x3
521 #define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)
570 #define RG_AUDACCDETRSV_MASK 0x3
571 #define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)
589 #define ACCDET_EINT0_SEQ_INIT_SFT 3
591 #define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)
654 #define ACCDET_EINT_EN_PWM_EN_SFT 3
656 #define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)
705 #define ACCDET_PWM_EN_SEL_MASK 0x3
706 #define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14)
745 #define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3
746 #define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4)
755 #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3
756 #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12)
815 #define ACCDET_IVAL_CUR_IN_MASK 0x3
816 #define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0)
820 #define ACCDET_IVAL_SAM_IN_MASK 0x3
821 #define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2)
825 #define ACCDET_IVAL_MEM_IN_MASK 0x3
826 #define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4)
830 #define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3
831 #define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6)
835 #define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3
836 #define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8)
840 #define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3
841 #define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10)
869 #define ACCDET_EINT_INVERTER_IVAL_SEL_SFT 3
871 #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)
884 #define ACCDET_EINT1_IRQ_SFT 3
886 #define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)
929 #define ACCDET_EINT0_CMPMEN_STABLE_SFT 3
931 #define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)
975 #define ACCDET_HWMODE_SEL_MASK 0x3
976 #define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1)
979 #define ACCDET_PLUG_OUT_DETECT_SFT 3
981 #define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)
1029 #define ACCDET_EINT_TEST_EN_SFT 3
1031 #define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)
1099 #define ACCDET_EINT_EN_SEL_SFT 3
1101 #define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)
1164 #define ACCDET_EINT0_EN_SW_SFT 3
1166 #define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)
1229 #define ACCDET_EINT0_CMPMOUT_SW_SFT 3
1231 #define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)
1265 #define ACCDET_CUR_IN_MASK 0x3
1266 #define ACCDET_CUR_IN_MASK_SFT (0x3 << 2)
1270 #define ACCDET_SAM_IN_MASK 0x3
1271 #define ACCDET_SAM_IN_MASK_SFT (0x3 << 4)
1275 #define ACCDET_MEM_IN_MASK 0x3
1276 #define ACCDET_MEM_IN_MASK_SFT (0x3 << 6)
1315 #define ACCDET_EINT0_CUR_IN_MASK 0x3
1316 #define ACCDET_EINT0_CUR_IN_MASK_SFT (0x3 << 2)
1320 #define ACCDET_EINT0_SAM_IN_MASK 0x3
1321 #define ACCDET_EINT0_SAM_IN_MASK_SFT (0x3 << 4)
1325 #define ACCDET_EINT0_MEM_IN_MASK 0x3
1326 #define ACCDET_EINT0_MEM_IN_MASK_SFT (0x3 << 6)
1360 #define ACCDET_EINT1_CUR_IN_MASK 0x3
1361 #define ACCDET_EINT1_CUR_IN_MASK_SFT (0x3 << 2)
1365 #define ACCDET_EINT1_SAM_IN_MASK 0x3
1366 #define ACCDET_EINT1_SAM_IN_MASK_SFT (0x3 << 4)
1370 #define ACCDET_EINT1_MEM_IN_MASK 0x3
1371 #define ACCDET_EINT1_MEM_IN_MASK_SFT (0x3 << 6)
1409 #define ACCDET_EINT0_INVERTER_MEM_IN_SFT 3
1411 #define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1449 #define ACCDET_EINT1_INVERTER_MEM_IN_SFT 3
1451 #define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1489 #define ACCDET_EINT0_M_EN_SFT 3
1491 #define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3)
1569 #define AD_EINT0CMPOUT_MON_SFT 3
1571 #define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3)
1609 #define DA_AUDACCDETAUXADCSWCTRL_MON_SFT 3
1611 #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3)
1629 #define DA_EINT0INVEN_MON_SFT 3
1631 #define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3)
1828 #define RG_AUDIF_CK_CKSEL_SFT 3
1830 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
1855 #define RG_AUDIF_CK_TSTSEL_SFT 3
1857 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
1881 #define RG_AUDNCP_RST_SFT 3
1883 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
1944 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
1945 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
1975 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
1976 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
1997 #define ADDA6_UL_SINE_ON_SFT 3
1999 #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
2023 #define PDN_I2S_DL_CTL_SFT 3
2025 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
2038 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
2039 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
2078 #define CCI_AUD_SDM_MUTEL_SFT 3
2080 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
2109 #define CCI_AUDIO_FIFO_ENABLE_SFT 3
2111 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
2152 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
2154 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2175 #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
2176 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
2178 #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
2179 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
2180 #define R_AUD_DAC_MONO_SEL_SFT 3
2182 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
2209 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
2211 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2261 #define CCI_AUD_SDM_MUTEL_2ND_SFT 3
2263 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
2292 #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 3
2294 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
2442 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
2443 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
2450 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT 3
2452 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
2473 #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3
2475 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
2518 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3
2520 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
2560 #define R_AUD_SDM_MUTE_L_2ND_SFT 3
2562 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
2605 #define DCCLK_REF_CK_SEL_MASK 0x3
2606 #define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)
2616 #define RESYNC_SRC_SEL_MASK 0x3
2617 #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
2708 #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3
2709 #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)
2711 #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3
2712 #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)
2714 #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3
2715 #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)
2717 #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3
2718 #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)
2720 #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3
2721 #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)
2723 #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3
2724 #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)
2739 #define RG_ADDA6_CH2_SEL_MASK 0x3
2740 #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)
2742 #define RG_ADDA6_CH1_SEL_MASK 0x3
2743 #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)
2748 #define RG_ADDA_CH2_SEL_MASK 0x3
2749 #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)
2751 #define RG_ADDA_CH1_SEL_MASK 0x3
2752 #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)
2808 #define RG_AUDPREAMPLPGATEST_SFT 3
2810 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
2812 #define RG_AUDPREAMPLVSCALE_MASK 0x3
2813 #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
2815 #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
2816 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
2827 #define RG_AUDADCLINPUTSEL_MASK 0x3
2828 #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
2840 #define RG_AUDPREAMPRPGATEST_SFT 3
2842 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
2844 #define RG_AUDPREAMPRVSCALE_MASK 0x3
2845 #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
2847 #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
2848 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
2859 #define RG_AUDADCRINPUTSEL_MASK 0x3
2860 #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
2872 #define RG_AUDPREAMP3PGATEST_SFT 3
2874 #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
2876 #define RG_AUDPREAMP3VSCALE_MASK 0x3
2877 #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)
2879 #define RG_AUDPREAMP3INPUTSEL_MASK 0x3
2880 #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)
2891 #define RG_AUDADC3INPUTSEL_MASK 0x3
2892 #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)
2904 #define RG_AUDADC1STSTAGELPEN_SFT 3
2906 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2914 #define RG_AUDPREAMPIDDTEST_MASK 0x3
2915 #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
2917 #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
2918 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
2920 #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
2921 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
2923 #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
2924 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
2926 #define RG_AUDADCFLASHIDDTEST_MASK 0x3
2927 #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
2939 #define RG_AUDRADC1STSTAGELPEN_SFT 3
2941 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2949 #define RG_AUDRPREAMPIDDTEST_MASK 0x3
2950 #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)
2952 #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3
2953 #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
2955 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3
2956 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
2958 #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3
2959 #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
2961 #define RG_AUDRADCFLASHIDDTEST_MASK 0x3
2962 #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
2969 #define RG_AUDADCCLKSEL_MASK 0x3
2970 #define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)
2971 #define RG_AUDADCCLKSOURCE_SFT 3
2972 #define RG_AUDADCCLKSOURCE_MASK 0x3
2973 #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)
2975 #define RG_AUDADCCLKGENMODE_MASK 0x3
2976 #define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)
3003 #define RG_AUDADCFSRESET_SFT 3
3005 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
3022 #define RG_AUDADCDACIDDTEST_MASK 0x3
3023 #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
3099 #define RG_AUDENC_SPARE2_SFT 3
3101 #define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)
3108 #define RG_AUDDIGMICBIAS_MASK 0x3
3109 #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
3110 #define RG_DMICHPCLKEN_SFT 3
3112 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
3114 #define RG_AUDDIGMICPDUTY_MASK 0x3
3115 #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
3117 #define RG_AUDDIGMICNDUTY_MASK 0x3
3118 #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
3131 #define RG_AUDDIGMICBIAS1_MASK 0x3
3132 #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)
3133 #define RG_DMIC1HPCLKEN_SFT 3
3135 #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
3137 #define RG_AUDDIGMIC1PDUTY_MASK 0x3
3138 #define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)
3140 #define RG_AUDDIGMIC1NDUTY_MASK 0x3
3141 #define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)
3162 #define RG_AUDPWDBMICBIAS3_SFT 3
3164 #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
3252 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
3254 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
3337 #define RG_EINT0CEN_SFT 3
3339 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
3388 #define RG_AUDIO_VOW_EN_SFT 3
3390 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
3414 #define RG_AUD_DAC_PWL_UP_VA32_SFT 3
3416 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
3430 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x3
3431 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)
3433 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x3
3434 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)
3458 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT 3
3460 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
3534 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x3
3535 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)
3556 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x3
3557 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
3591 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x3
3592 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
3629 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x3
3630 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)
3635 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x3
3636 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)
3638 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x3
3639 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)
3664 #define RG_AUDZCDCLKSEL_VAUDP32_SFT 3
3666 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
3727 #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
3728 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
4009 #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
4013 #define IBIAS_MASK 0x3
4064 MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */
4101 RCV_MUX_MASK = 0x3,
4109 LO_MUX_MASK = 0x3,
4256 /* PGA 3 MUX */