Lines Matching +full:0 +full:xfff7
24 regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0); in mt6359_set_gpio_smt()
30 regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888); in mt6359_set_gpio_driving()
31 regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888); in mt6359_set_gpio_driving()
32 regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88); in mt6359_set_gpio_driving()
38 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe); in mt6359_set_playback_gpio()
39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249); in mt6359_set_playback_gpio()
42 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6); in mt6359_set_playback_gpio()
43 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1); in mt6359_set_playback_gpio()
53 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8); in mt6359_reset_playback_gpio()
54 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0); in mt6359_reset_playback_gpio()
60 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); in mt6359_set_capture_gpio()
61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200); in mt6359_set_capture_gpio()
63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); in mt6359_set_capture_gpio()
64 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009); in mt6359_set_capture_gpio()
75 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); in mt6359_reset_capture_gpio()
77 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); in mt6359_reset_capture_gpio()
80 0x7 << 13, 0x0); in mt6359_reset_capture_gpio()
82 0x3 << 0, 0x0); in mt6359_reset_capture_gpio()
89 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6359_set_dcxo()
90 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); in mt6359_set_dcxo()
99 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); in mt6359_set_clksq()
107 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT); in mt6359_set_aud_global_bias()
114 0x0066, enable ? 0x0 : 0x66); in mt6359_set_topck()
121 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT); in mt6359_set_decoder_clk()
131 0xffff, 0x0210); in mt6359_mtkaif_tx_enable()
135 0xff00, 0x3800); in mt6359_mtkaif_tx_enable()
138 0xff00, 0x3900); in mt6359_mtkaif_tx_enable()
144 0xffff, 0x0210); in mt6359_mtkaif_tx_enable()
148 0xff00, 0x3100); in mt6359_mtkaif_tx_enable()
155 0xffff, 0x0000); in mt6359_mtkaif_tx_enable()
159 0xff00, 0x3100); in mt6359_mtkaif_tx_enable()
168 0xff00, 0x3000); in mt6359_mtkaif_tx_disable()
213 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); in mt6359_mtkaif_calibration_disable()
216 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); in mt6359_mtkaif_calibration_disable()
219 0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT); in mt6359_mtkaif_calibration_disable()
251 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000); in zcd_disable()
260 for (i = 0; i <= target; i++) { in hp_main_output_ramp()
275 int target = 0xf; in hp_aux_feedback_loop_gain_ramp()
278 for (i = 0; i <= target; i++) { in hp_aux_feedback_loop_gain_ramp()
281 0xf << 12, stage << 12); in hp_aux_feedback_loop_gain_ramp()
289 int target = 0x3; in hp_in_pair_current()
294 for (i = 0; i <= target; i++) { in hp_in_pair_current()
298 0x3 << 3, stage << 3); in hp_in_pair_current()
309 for (i = 0x0; i <= 0x7; i++) { in hp_pull_down()
316 for (i = 0x7; i >= 0x0; i--) { in hp_pull_down()
334 int offset = 0, count = 1, reg_idx; in headset_volume_ramp()
349 while (offset > 0) { in headset_volume_ramp()
375 unsigned int reg = 0; in mt6359_put_volsw()
376 int index = ucontrol->value.integer.value[0]; in mt6359_put_volsw()
382 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; in mt6359_put_volsw()
386 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]; in mt6359_put_volsw()
390 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]; in mt6359_put_volsw()
393 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; in mt6359_put_volsw()
396 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; in mt6359_put_volsw()
399 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; in mt6359_put_volsw()
406 if (ret < 0) in mt6359_put_volsw()
416 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]; in mt6359_put_volsw()
425 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]; in mt6359_put_volsw()
432 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]; in mt6359_put_volsw()
438 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; in mt6359_put_volsw()
444 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; in mt6359_put_volsw()
450 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3]; in mt6359_put_volsw()
454 ret = 0; in mt6359_put_volsw()
455 if (orig_gain[0] != new_gain[0]) { in mt6359_put_volsw()
462 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n", in mt6359_put_volsw()
479 ucontrol->value.integer.value[0] = in mt6359_get_playback_volsw()
485 ucontrol->value.integer.value[0] = in mt6359_get_playback_volsw()
491 ucontrol->value.integer.value[0] = in mt6359_get_playback_volsw()
498 return 0; in mt6359_get_playback_volsw()
508 static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);
524 0,
537 0,
549 0x0, 0x1,
823 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
828 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
830 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); in mt_sgen_event()
832 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
834 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b); in mt_sgen_event()
837 0xff3f, in mt_sgen_event()
838 0x0000); in mt_sgen_event()
840 0xffff, in mt_sgen_event()
841 0x0001); in mt_sgen_event()
845 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
846 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
852 return 0; in mt_sgen_event()
887 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087); in mtk_hp_enable()
895 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT); in mtk_hp_enable()
897 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000); in mtk_hp_enable()
900 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133); in mtk_hp_enable()
903 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
907 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
909 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
911 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
913 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
919 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
921 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
924 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
931 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); in mtk_hp_enable()
939 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); in mtk_hp_enable()
941 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703); in mtk_hp_enable()
948 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
951 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
954 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); in mtk_hp_enable()
959 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
961 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
974 0x0f00, 0x0000); in mtk_hp_disable()
978 0x0001, 0x0000); in mtk_hp_disable()
982 0x000f, 0x0000); in mtk_hp_disable()
988 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); in mtk_hp_disable()
990 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); in mtk_hp_disable()
998 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff); in mtk_hp_disable()
1007 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1010 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01); in mtk_hp_disable()
1013 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01); in mtk_hp_disable()
1020 0x3 << 6, 0x0); in mtk_hp_disable()
1024 0x3 << 4, 0x0); in mtk_hp_disable()
1028 0x3 << 6, 0x0); in mtk_hp_disable()
1031 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201); in mtk_hp_disable()
1035 0x3 << 4, 0x0); in mtk_hp_disable()
1039 0x3 << 2, 0x0); in mtk_hp_disable()
1048 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1051 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1069 return 0; in mt_hp_event()
1079 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1080 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1085 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1101 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1104 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000); in mt_rcv_event()
1107 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1109 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1119 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1121 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1123 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1133 0x000f, 0x0000); in mt_rcv_event()
1143 RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0); in mt_rcv_event()
1147 RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); in mt_rcv_event()
1153 return 0; in mt_rcv_event()
1162 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_lo_event()
1164 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_lo_event()
1170 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010); in mt_lo_event()
1178 if (priv->dev_counter[DEVICE_HP] == 0) in mt_lo_event()
1189 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110); in mt_lo_event()
1192 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112); in mt_lo_event()
1194 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113); in mt_lo_event()
1205 if (priv->dev_counter[DEVICE_HP] > 0) { in mt_lo_event()
1211 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3009); in mt_lo_event()
1213 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); in mt_lo_event()
1216 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0117); in mt_lo_event()
1219 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113); in mt_lo_event()
1221 if (priv->dev_counter[DEVICE_HP] == 0) in mt_lo_event()
1222 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); in mt_lo_event()
1224 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b); in mt_lo_event()
1235 0x000f, 0x0000); in mt_lo_event()
1240 0x3 << 4, 0x0); in mt_lo_event()
1243 0x3 << 6, 0x0); in mt_lo_event()
1254 RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0); in mt_lo_event()
1258 RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); in mt_lo_event()
1264 return 0; in mt_lo_event()
1274 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); in mt_adc_clk_gen_event()
1281 0x1 << RG_AUDADCCLKRSTB_SFT); in mt_adc_clk_gen_event()
1283 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1285 RG_AUDADCCLKSEL_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1288 0x1 << RG_AUDADCCLKGENMODE_SFT); in mt_adc_clk_gen_event()
1292 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1294 RG_AUDADCCLKSEL_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1296 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1298 RG_AUDADCCLKRSTB_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1304 return 0; in mt_adc_clk_gen_event()
1314 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); in mt_dcc_clk_event()
1321 0xfff7, 0x2062); in mt_dcc_clk_event()
1323 0xfff7, 0x2060); in mt_dcc_clk_event()
1325 0xfff7, 0x2061); in mt_dcc_clk_event()
1327 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100); in mt_dcc_clk_event()
1331 0xfff7, 0x2060); in mt_dcc_clk_event()
1333 0xfff7, 0x2062); in mt_dcc_clk_event()
1339 return 0; in mt_dcc_clk_event()
1350 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_0_event()
1359 0xff00, 0x7700); in mt_mic_bias_0_event()
1364 0xff00, 0x1100); in mt_mic_bias_0_event()
1369 0xff00, 0x0000); in mt_mic_bias_0_event()
1375 MT6359_AUDENC_ANA_CON14, 0x0004); in mt_mic_bias_0_event()
1383 0 << RG_AUDMICBIAS0LOWPEN_SFT); in mt_mic_bias_0_event()
1387 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000); in mt_mic_bias_0_event()
1393 return 0; in mt_mic_bias_0_event()
1404 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_1_event()
1412 MT6359_AUDENC_ANA_CON16, 0x0160); in mt_mic_bias_1_event()
1415 MT6359_AUDENC_ANA_CON16, 0x0060); in mt_mic_bias_1_event()
1420 0 << RG_AUDMICBIAS1LOWPEN_SFT); in mt_mic_bias_1_event()
1426 return 0; in mt_mic_bias_1_event()
1437 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_2_event()
1446 0xff00, 0x7700); in mt_mic_bias_2_event()
1451 0xff00, 0x1100); in mt_mic_bias_2_event()
1456 0xff00, 0x0000); in mt_mic_bias_2_event()
1467 0 << RG_AUDMICBIAS2LOWPEN_SFT); in mt_mic_bias_2_event()
1471 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000); in mt_mic_bias_2_event()
1477 return 0; in mt_mic_bias_2_event()
1487 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_mtkaif_tx_event()
1500 return 0; in mt_mtkaif_tx_event()
1510 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_ul_src_dmic_event()
1517 0x0400); in mt_ul_src_dmic_event()
1520 0x0080); in mt_ul_src_dmic_event()
1523 0xfffc, 0x0000); in mt_ul_src_dmic_event()
1527 MT6359_AFE_UL_SRC_CON0_H, 0x0000); in mt_ul_src_dmic_event()
1533 return 0; in mt_ul_src_dmic_event()
1543 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_ul_src_34_dmic_event()
1549 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080); in mt_ul_src_34_dmic_event()
1551 0xfffc, 0x0000); in mt_ul_src_34_dmic_event()
1555 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000); in mt_ul_src_34_dmic_event()
1561 return 0; in mt_ul_src_34_dmic_event()
1571 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_l_event()
1579 0x0); in mt_adc_l_event()
1585 return 0; in mt_adc_l_event()
1595 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_r_event()
1603 0x0); in mt_adc_r_event()
1609 return 0; in mt_adc_r_event()
1619 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_3_event()
1627 0x0); in mt_adc_3_event()
1633 return 0; in mt_adc_3_event()
1642 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_l_mux_event()
1646 return 0; in mt_pga_l_mux_event()
1655 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_r_mux_event()
1659 return 0; in mt_pga_r_mux_event()
1668 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_3_mux_event()
1672 return 0; in mt_pga_3_mux_event()
1704 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT); in mt_pga_l_event()
1717 0x1 << RG_AUDPREAMPLDCCEN_SFT); in mt_pga_l_event()
1724 0x0 << RG_AUDPREAMPLDCCEN_SFT); in mt_pga_l_event()
1730 return 0; in mt_pga_l_event()
1763 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT); in mt_pga_r_event()
1776 0x1 << RG_AUDPREAMPRDCCEN_SFT); in mt_pga_r_event()
1783 0x0 << RG_AUDPREAMPRDCCEN_SFT); in mt_pga_r_event()
1789 return 0; in mt_pga_r_event()
1819 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT); in mt_pga_3_event()
1832 0x1 << RG_AUDPREAMP3DCCEN_SFT); in mt_pga_3_event()
1839 0x0 << RG_AUDPREAMP3DCCEN_SFT); in mt_pga_3_event()
1845 return 0; in mt_pga_3_event()
1862 return 0; in mt_delay_250_event()
1878 return 0; in mt_delay_100_event()
1899 return 0; in mt_hp_pull_down_event()
1922 return 0; in mt_hp_mute_event()
1936 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000); in mt_hp_damp_event()
1942 return 0; in mt_hp_damp_event()
1957 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT); in mt_esd_resist_event()
1963 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0); in mt_esd_resist_event()
1969 return 0; in mt_esd_resist_event()
1983 0xfffd, 0x0006); in mt_sdm_event()
1985 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); in mt_sdm_event()
1988 0xfffd, 0x0003); in mt_sdm_event()
1991 0xfffd, 0x000B); in mt_sdm_event()
1996 0xfffd, 0x0000); in mt_sdm_event()
1997 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); in mt_sdm_event()
2003 return 0; in mt_sdm_event()
2016 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006); in mt_sdm_3rd_event()
2018 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1); in mt_sdm_3rd_event()
2020 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003); in mt_sdm_3rd_event()
2022 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b); in mt_sdm_3rd_event()
2026 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000); in mt_sdm_3rd_event()
2027 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0); in mt_sdm_3rd_event()
2033 return 0; in mt_sdm_3rd_event()
2045 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800); in mt_ncp_event()
2051 return 0; in mt_ncp_event()
2059 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2062 RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
2065 RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU),
2068 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2071 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2078 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2079 SND_SOC_DAPM_REGULATOR_SUPPLY("vaud18", 0, 0),
2089 PDN_DAC_CTL_SFT, 1, NULL, 0),
2092 PDN_ADC_CTL_SFT, 1, NULL, 0),
2095 PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
2098 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2101 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2104 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2107 PDN_RESERVED_SFT, 1, NULL, 0),
2110 SND_SOC_NOPM, 0, 0,
2114 SND_SOC_NOPM, 0, 0,
2121 CCI_AFIFO_CLK_PWDB_SFT, 0,
2122 NULL, 0),
2126 RG_NCP_ON_SFT, 0,
2131 0, 0, NULL, 0),
2133 0, 0, NULL, 0),
2135 0, 0, NULL, 0),
2139 MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2140 NULL, 0),
2143 SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
2144 SND_SOC_NOPM, 0, 0),
2146 SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
2147 SND_SOC_NOPM, 0, 0),
2151 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2152 NULL, 0),
2156 0, 0, NULL, 0),
2160 0, 0,
2165 RG_LCLDO_DEC_EN_VA32_SFT, 0,
2166 NULL, 0),
2169 RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
2170 NULL, 0),
2173 RG_NVREG_EN_VAUDP32_SFT, 0,
2178 NULL, 0),
2181 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2183 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2185 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2187 SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
2190 SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0,
2196 0, 0, NULL, 0),
2199 0, 0,
2204 0, 0,
2209 0, 0,
2214 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2220 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
2235 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2241 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2246 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
2247 SND_SOC_NOPM, 0, 0),
2248 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
2249 SND_SOC_NOPM, 0, 0),
2252 SND_SOC_NOPM, 0, 0,
2257 SND_SOC_NOPM, 0, 0,
2262 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2265 SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
2268 SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
2271 SND_SOC_NOPM, 0, 0,
2277 UL_SRC_ON_TMP_CTL_SFT, 0,
2278 NULL, 0),
2281 SND_SOC_NOPM, 0, 0,
2287 ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
2288 NULL, 0),
2291 SND_SOC_NOPM, 0, 0,
2295 SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
2296 SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
2297 SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
2299 SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
2301 SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
2304 SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
2305 SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
2306 SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
2308 SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
2309 &adc_left_mux_control, NULL, 0),
2310 SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
2311 &adc_right_mux_control, NULL, 0),
2312 SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
2313 &adc_3_mux_control, NULL, 0),
2315 SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
2316 SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
2317 SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
2321 RG_AUDADCLPWRUP_SFT, 0,
2326 RG_AUDADCRPWRUP_SFT, 0,
2331 RG_AUDADC3PWRUP_SFT, 0,
2335 SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
2339 SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
2343 SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
2348 SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
2349 SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
2350 SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
2354 RG_AUDPREAMPLON_SFT, 0,
2361 RG_AUDPREAMPRON_SFT, 0,
2368 RG_AUDPREAMP3ON_SFT, 0,
2387 RG_AUDPWDBMICBIAS0_SFT, 0,
2392 RG_AUDPWDBMICBIAS1_SFT, 0,
2397 RG_AUDPWDBMICBIAS2_SFT, 0,
2404 RG_AUDDIGMICEN_SFT, 0,
2405 NULL, 0),
2408 RG_AUDDIGMIC1EN_SFT, 0,
2409 NULL, 0),
2424 return 0; in mt_dcc_clk_connect()
2661 return 0; in mt6359_codec_dai_hw_params()
2676 return 0; in mt6359_codec_dai_startup()
2761 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6359_codec_init_reg()
2762 0x1 << RG_XO_AUDIO_EN_M_SFT); in mt6359_codec_init_reg()
2769 0x0); in mt6359_codec_init_reg()
2774 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2777 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2781 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2785 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2794 priv->hp_hifi_mode = 0; in mt6359_codec_init_reg()
2801 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6359_codec_init_reg()
2802 0x0 << RG_XO_AUDIO_EN_M_SFT); in mt6359_codec_init_reg()
2804 return 0; in mt6359_codec_init_reg()
2821 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
2822 static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
2827 MT6359_ZCD_CON2, 0, 7, 0x12, 0,
2831 MT6359_ZCD_CON1, 0, 7, 0x12, 0,
2835 MT6359_ZCD_CON3, 0, 0x12, 0,
2841 MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
2844 MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
2847 MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
2878 "%s() failed to read dmic-mode, use default (0)\n", in mt6359_parse_dt()
2880 priv->dmic_one_wire_mode = 0; in mt6359_parse_dt()
2883 ret = of_property_read_u32(np, "mediatek,mic-type-0", in mt6359_parse_dt()
2887 "%s() failed to read mic-type-0, use default (%d)\n", in mt6359_parse_dt()
2911 return 0; in mt6359_parse_dt()