Lines Matching +full:0 +full:x2500
74 CH_L = 0,
108 return 0; in mt6358_set_mtkaif_protocol()
116 0x01f8, 0x01f8); in playback_gpio_set()
118 0xffff, 0x0249); in playback_gpio_set()
120 0xffff, 0x0249); in playback_gpio_set()
131 0x01f8, 0x01f8); in playback_gpio_reset()
133 0x01f8, 0x0000); in playback_gpio_reset()
135 0xf << 8, 0x0); in playback_gpio_reset()
142 0xffff, 0xffff); in capture_gpio_set()
144 0xffff, 0x0249); in capture_gpio_set()
146 0xffff, 0x0249); in capture_gpio_set()
158 0xffff, 0xffff); in capture_gpio_reset()
160 0xffff, 0x0000); in capture_gpio_reset()
162 0xf << 12, 0x0); in capture_gpio_reset()
169 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6358_set_dcxo()
170 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); in mt6358_set_dcxo()
171 return 0; in mt6358_set_dcxo()
180 0x0); in mt6358_set_clksq()
185 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); in mt6358_set_clksq()
186 return 0; in mt6358_set_clksq()
194 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); in mt6358_set_aud_global_bias()
195 return 0; in mt6358_set_aud_global_bias()
202 0x0066, enable ? 0x0 : 0x66); in mt6358_set_topck()
203 return 0; in mt6358_set_topck()
213 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
217 0xff00, 0x3800); in mt6358_mtkaif_tx_enable()
220 0xff00, 0x3900); in mt6358_mtkaif_tx_enable()
226 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
230 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
237 0xffff, 0x0000); in mt6358_mtkaif_tx_enable()
241 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
244 return 0; in mt6358_mtkaif_tx_enable()
251 0xff00, 0x3000); in mt6358_mtkaif_tx_disable()
252 return 0; in mt6358_mtkaif_tx_disable()
275 return 0; in mt6358_mtkaif_calibration_enable()
286 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
289 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
299 return 0; in mt6358_mtkaif_calibration_disable()
314 return 0; in mt6358_set_mtkaif_calibration_phase()
320 DL_GAIN_8DB = 0,
324 DL_GAIN_N_40DB = 0x1f,
329 #define DL_GAIN_REG_MASK 0x0f9f
333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
342 for (i = 0; i <= target; i++) { in hp_main_output_ramp()
345 0x7 << 8, stage << 8); in hp_main_output_ramp()
347 0x7 << 11, stage << 11); in hp_main_output_ramp()
357 for (i = 0; i <= 0xf; i++) { in hp_aux_feedback_loop_gain_ramp()
358 stage = up ? i : 0xf - i; in hp_aux_feedback_loop_gain_ramp()
360 0xf << 12, stage << 12); in hp_aux_feedback_loop_gain_ramp()
370 for (i = 0x0; i <= 0x6; i++) { in hp_pull_down()
372 0x7, i); in hp_pull_down()
376 for (i = 0x6; i >= 0x1; i--) { in hp_pull_down()
378 0x7, i); in hp_pull_down()
392 int offset = 0, count = 0, reg_idx; in headset_volume_ramp()
406 while (offset >= 0) { in headset_volume_ramp()
432 unsigned int reg = 0; in mt6358_put_volsw()
436 if (ret < 0) in mt6358_put_volsw()
481 0xffff, 0x0000); in mt6358_enable_wov_phase2()
482 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_enable_wov_phase2()
484 0xffff, 0x0800); in mt6358_enable_wov_phase2()
487 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); in mt6358_enable_wov_phase2()
489 0xffff, 0x0025); in mt6358_enable_wov_phase2()
491 0xffff, 0x0005); in mt6358_enable_wov_phase2()
495 0xffff, 0x0000); in mt6358_enable_wov_phase2()
496 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); in mt6358_enable_wov_phase2()
497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); in mt6358_enable_wov_phase2()
498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); in mt6358_enable_wov_phase2()
499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); in mt6358_enable_wov_phase2()
500 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); in mt6358_enable_wov_phase2()
501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); in mt6358_enable_wov_phase2()
502 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); in mt6358_enable_wov_phase2()
504 0xffff, 0x0000); in mt6358_enable_wov_phase2()
506 0xffff, 0x0451); in mt6358_enable_wov_phase2()
507 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); in mt6358_enable_wov_phase2()
509 return 0; in mt6358_enable_wov_phase2()
515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); in mt6358_disable_wov_phase2()
517 0xffff, 0x0450); in mt6358_disable_wov_phase2()
519 0xffff, 0x0c00); in mt6358_disable_wov_phase2()
520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); in mt6358_disable_wov_phase2()
521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); in mt6358_disable_wov_phase2()
522 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); in mt6358_disable_wov_phase2()
523 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); in mt6358_disable_wov_phase2()
524 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); in mt6358_disable_wov_phase2()
525 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); in mt6358_disable_wov_phase2()
526 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); in mt6358_disable_wov_phase2()
528 0xffff, 0x0000); in mt6358_disable_wov_phase2()
532 0xffff, 0x0004); in mt6358_disable_wov_phase2()
534 0xffff, 0x0000); in mt6358_disable_wov_phase2()
535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); in mt6358_disable_wov_phase2()
537 0xffff, 0x0000); in mt6358_disable_wov_phase2()
539 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_disable_wov_phase2()
541 0xffff, 0x0010); in mt6358_disable_wov_phase2()
543 return 0; in mt6358_disable_wov_phase2()
552 ucontrol->value.integer.value[0] = priv->wov_enabled; in mt6358_get_wov()
553 return 0; in mt6358_get_wov()
561 int enabled = ucontrol->value.integer.value[0]; in mt6358_put_wov()
563 if (enabled < 0 || enabled > 1) in mt6358_put_wov()
577 return 0; in mt6358_put_wov()
586 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode; in mt6358_dmic_mode_get()
589 return 0; in mt6358_dmic_mode_get()
597 int enabled = ucontrol->value.integer.value[0]; in mt6358_dmic_mode_set()
599 if (enabled < 0 || enabled > 1) in mt6358_dmic_mode_set()
610 return 0; in mt6358_dmic_mode_set()
613 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
614 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
619 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
622 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
625 MT6358_ZCD_CON3, 0, 0x12, 1,
630 8, 4, 0,
633 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
636 SOC_SINGLE_BOOL_EXT("Dmic Mode Switch", 0,
647 0x0, 0x1, 0x2, 0x3,
662 HP_MUX_OPEN = 0,
667 HP_MUX_MASK = 0x7,
688 0,
698 0,
708 RCV_MUX_OPEN = 0,
712 RCV_MUX_MASK = 0x3,
728 0,
742 0x0, 0x1,
768 MIC_TYPE_MUX_IDLE = 0,
774 MIC_TYPE_MUX_MASK = 0x7,
801 0,
811 ADC_MUX_IDLE = 0,
815 ADC_MUX_MASK = 0x3,
831 0,
846 0,
856 PGA_MUX_NONE = 0,
860 PGA_MUX_MASK = 0x3,
876 0,
887 0,
902 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_clksq_event()
909 0x0); in mt_clksq_event()
915 return 0; in mt_clksq_event()
925 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
930 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
932 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
934 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
936 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
939 0xff3f, in mt_sgen_event()
940 0x0000); in mt_sgen_event()
942 0xffff, in mt_sgen_event()
943 0x0001); in mt_sgen_event()
947 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
948 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
954 return 0; in mt_sgen_event()
964 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
972 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
974 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
976 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
978 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_aif_in_event()
982 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_aif_in_event()
983 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_aif_in_event()
991 return 0; in mt_aif_in_event()
1000 0x1 << 6, 0x1 << 6); in mtk_hp_enable()
1003 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_enable()
1009 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_enable()
1011 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_enable()
1013 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_enable()
1015 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_enable()
1017 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_enable()
1022 0x1055, 0x1055); in mtk_hp_enable()
1024 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_enable()
1031 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_enable()
1034 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1037 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_enable()
1040 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1042 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_enable()
1045 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
1047 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
1049 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
1051 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
1053 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
1055 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
1058 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
1060 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
1064 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_enable()
1067 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
1074 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_enable()
1082 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_enable()
1084 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); in mtk_hp_enable()
1088 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_enable()
1090 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
1092 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
1096 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
1098 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
1103 return 0; in mtk_hp_enable()
1113 0x0f00, 0x0000); in mtk_hp_disable()
1117 0x0001, 0x0000); in mtk_hp_disable()
1121 0x000f, 0x0000); in mtk_hp_disable()
1124 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_disable()
1127 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_disable()
1129 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_disable()
1137 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_disable()
1146 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1149 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_disable()
1152 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_disable()
1156 0x3 << 6, 0x0); in mtk_hp_disable()
1160 0x3 << 4, 0x0); in mtk_hp_disable()
1164 0x3 << 6, 0x0); in mtk_hp_disable()
1167 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mtk_hp_disable()
1171 0x3 << 4, 0x0); in mtk_hp_disable()
1175 0x3 << 2, 0x0); in mtk_hp_disable()
1179 0x1 << 8, 0x1 << 8); in mtk_hp_disable()
1182 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_disable()
1185 0x1055, 0x0); in mtk_hp_disable()
1188 0x1, 0x1); in mtk_hp_disable()
1192 0x1 << 14, 0x0); in mtk_hp_disable()
1196 0x1 << 6, 0x0); in mtk_hp_disable()
1200 return 0; in mtk_hp_disable()
1209 0x1 << 6, 0x1 << 6); in mtk_hp_spk_enable()
1212 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_spk_enable()
1218 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_spk_enable()
1220 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_spk_enable()
1222 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_spk_enable()
1224 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_spk_enable()
1226 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_spk_enable()
1231 0x1055, 0x1055); in mtk_hp_spk_enable()
1233 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_spk_enable()
1240 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_spk_enable()
1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1246 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_spk_enable()
1249 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1251 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_spk_enable()
1257 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_spk_enable()
1259 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_spk_enable()
1261 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_spk_enable()
1265 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_spk_enable()
1268 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); in mtk_hp_spk_enable()
1280 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); in mtk_hp_spk_enable()
1282 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); in mtk_hp_spk_enable()
1284 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); in mtk_hp_spk_enable()
1297 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_spk_enable()
1299 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); in mtk_hp_spk_enable()
1301 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); in mtk_hp_spk_enable()
1303 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); in mtk_hp_spk_enable()
1305 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); in mtk_hp_spk_enable()
1307 return 0; in mtk_hp_spk_enable()
1314 0x0f00, 0x0000); in mtk_hp_spk_disable()
1317 0x3 << 2, 0x0000); in mtk_hp_spk_disable()
1321 0x000f, 0x0000); in mtk_hp_spk_disable()
1324 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_spk_disable()
1339 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_spk_disable()
1342 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_spk_disable()
1344 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_spk_disable()
1347 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_spk_disable()
1354 0x3 << 4, 0x0); in mtk_hp_spk_disable()
1357 0x1, 0x0); in mtk_hp_spk_disable()
1361 0x3 << 6, 0x0); in mtk_hp_spk_disable()
1364 0x1 << 1, 0x0); in mtk_hp_spk_disable()
1368 0xff << 8, 0x0000); in mtk_hp_spk_disable()
1372 0x1 << 8, 0x1 << 8); in mtk_hp_spk_disable()
1374 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_spk_disable()
1376 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); in mtk_hp_spk_disable()
1378 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); in mtk_hp_spk_disable()
1382 0x1 << 6, 0x0); in mtk_hp_spk_disable()
1386 return 0; in mtk_hp_spk_disable()
1395 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1398 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1409 else if (priv->dev_counter[device] <= 0) in mt_hp_event()
1410 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", in mt_hp_event()
1423 if (priv->dev_counter[device] > 0) { in mt_hp_event()
1425 } else if (priv->dev_counter[device] < 0) { in mt_hp_event()
1426 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", in mt_hp_event()
1429 priv->dev_counter[device] = 0; in mt_hp_event()
1444 return 0; in mt_hp_event()
1454 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1457 dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1462 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mt_rcv_event()
1465 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mt_rcv_event()
1467 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mt_rcv_event()
1469 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mt_rcv_event()
1471 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mt_rcv_event()
1473 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mt_rcv_event()
1478 0x1055, 0x1055); in mt_rcv_event()
1480 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mt_rcv_event()
1487 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1490 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1492 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mt_rcv_event()
1495 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1497 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1500 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mt_rcv_event()
1503 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mt_rcv_event()
1506 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1508 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1512 0x1, 0x1); in mt_rcv_event()
1515 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1517 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1519 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1529 0x000f, 0x0000); in mt_rcv_event()
1533 0x1, 0x0); in mt_rcv_event()
1540 0x1, 0x0); in mt_rcv_event()
1544 0x1 << 1, 0x0000); in mt_rcv_event()
1548 0xff << 8, 0x0); in mt_rcv_event()
1552 0xff << 8, 0x2 << 8); in mt_rcv_event()
1556 0x1 << 8, 0x1 << 8); in mt_rcv_event()
1560 0x1, 0x0); in mt_rcv_event()
1563 0x1055, 0x0); in mt_rcv_event()
1566 0x1, 0x1); in mt_rcv_event()
1572 return 0; in mt_rcv_event()
1582 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
1596 return 0; in mt_aif_out_event()
1606 dev_dbg(priv->dev, "%s(), event 0x%x\n", in mt_adc_supply_event()
1613 0x1 << 5, 0x1 << 5); in mt_adc_supply_event()
1616 0x0000); in mt_adc_supply_event()
1619 0x2500, 0x0100); in mt_adc_supply_event()
1622 0x2500, 0x2500); in mt_adc_supply_event()
1627 0x2500, 0x0100); in mt_adc_supply_event()
1630 0x2500, 0x0000); in mt_adc_supply_event()
1633 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); in mt_adc_supply_event()
1636 0x1 << 5, 0x0 << 5); in mt_adc_supply_event()
1642 return 0; in mt_adc_supply_event()
1656 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1657 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1658 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_enable()
1659 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); in mt6358_amic_enable()
1660 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); in mt6358_amic_enable()
1663 /* mic bias 0 */ in mt6358_amic_enable()
1669 0xff00, 0x7700); in mt6358_amic_enable()
1673 0xff00, 0x1100); in mt6358_amic_enable()
1677 0xff00, 0x0000); in mt6358_amic_enable()
1682 0xff, 0x21); in mt6358_amic_enable()
1690 MT6358_AUDENC_ANA_CON10, 0x0161); in mt6358_amic_enable()
1693 MT6358_AUDENC_ANA_CON10, 0x0061); in mt6358_amic_enable()
1699 0xf8ff, 0x0004); in mt6358_amic_enable()
1701 0xf8ff, 0x0004); in mt6358_amic_enable()
1705 0xf8ff, 0x0000); in mt6358_amic_enable()
1707 0xf8ff, 0x0000); in mt6358_amic_enable()
1719 0x1 << RG_AUDPREAMPLON_SFT); in mt6358_amic_enable()
1725 0x1 << RG_AUDPREAMPLDCCEN_SFT); in mt6358_amic_enable()
1735 0x1 << RG_AUDADCLPWRUP_SFT); in mt6358_amic_enable()
1747 0x1 << RG_AUDPREAMPRON_SFT); in mt6358_amic_enable()
1753 0x1 << RG_AUDPREAMPRDCCEN_SFT); in mt6358_amic_enable()
1763 0x1 << RG_AUDADCRPWRUP_SFT); in mt6358_amic_enable()
1770 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1773 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1777 0x1 << 12, 0x0); in mt6358_amic_enable()
1784 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); in mt6358_amic_enable()
1787 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); in mt6358_amic_enable()
1789 return 0; in mt6358_amic_enable()
1803 0x0001, 0x0000); in mt6358_amic_disable()
1810 0xf000, 0x0000); in mt6358_amic_disable()
1813 0x1 << 1, 0x0); in mt6358_amic_disable()
1814 /* L preamplifier input sel : off, L PGA 0 dB gain */ in mt6358_amic_disable()
1816 0xfffb, 0x0000); in mt6358_amic_disable()
1820 0x1 << 2, 0x0); in mt6358_amic_disable()
1824 0xf000, 0x0000); in mt6358_amic_disable()
1827 0x1 << 1, 0x0); in mt6358_amic_disable()
1828 /* R preamplifier input sel : off, R PGA 0 dB gain */ in mt6358_amic_disable()
1830 0x0ffb, 0x0000); in mt6358_amic_disable()
1834 0x1 << 2, 0x0); in mt6358_amic_disable()
1838 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_amic_disable()
1842 0x0001, 0x0000); in mt6358_amic_disable()
1846 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_disable()
1848 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1850 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1852 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1862 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); in mt6358_dmic_enable()
1866 0x1 << 12, 0x0); in mt6358_dmic_enable()
1869 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); in mt6358_dmic_enable()
1876 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); in mt6358_dmic_enable()
1878 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); in mt6358_dmic_enable()
1881 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); in mt6358_dmic_enable()
1886 return 0; in mt6358_dmic_enable()
1895 0x0003, 0x0000); in mt6358_dmic_disable()
1901 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); in mt6358_dmic_disable()
1905 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); in mt6358_dmic_disable()
1909 0x1 << 12, 0x0); in mt6358_dmic_disable()
1912 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_dmic_disable()
1936 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_mic_type_event()
1938 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_mic_type_event()
1973 return 0; in mt_mic_type_event()
1982 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_l_event()
1984 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_l_event()
1989 return 0; in mt_adc_l_event()
1998 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_r_event()
2000 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_r_event()
2005 return 0; in mt_adc_r_event()
2014 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_left_event()
2016 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_left_event()
2021 return 0; in mt_pga_left_event()
2030 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_right_event()
2032 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_right_event()
2037 return 0; in mt_pga_right_event()
2055 return 0; in mt_delay_250_event()
2063 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2066 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2069 RG_CLKSQ_EN_SFT, 0,
2074 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2077 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2085 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2095 PDN_DAC_CTL_SFT, 1, NULL, 0),
2098 PDN_ADC_CTL_SFT, 1, NULL, 0),
2101 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2104 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2107 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2110 PDN_RESERVED_SFT, 1, NULL, 0),
2113 0, 0, NULL, 0),
2117 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2118 NULL, 0),
2121 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2123 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2129 0, 0, NULL, 0),
2132 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2134 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2136 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2139 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2142 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2145 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2148 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2154 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2161 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2178 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2184 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2189 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2190 SND_SOC_NOPM, 0, 0,
2195 SND_SOC_NOPM, 0, 0,
2200 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2203 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2209 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2213 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2218 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2219 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2221 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2225 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2230 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2231 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2371 return 0; in mt6358_codec_dai_hw_params()
2413 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2416 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2420 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2424 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2428 0xFFFF, 0x700E); in mt6358_codec_init_reg()
2431 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); in mt6358_codec_init_reg()
2457 return 0; in mt6358_codec_probe()
2481 priv->dmic_one_wire_mode = 0; in mt6358_parse_dt()