Lines Matching +full:0 +full:x2140
17 #define MT6357_GPIO8_DIR_INPUT 0
20 #define MT6357_GPIO9_DIR_INPUT 0
23 #define MT6357_GPIO10_DIR_INPUT 0
26 #define MT6357_GPIO11_DIR_INPUT 0
29 #define MT6357_GPIO12_DIR_INPUT 0
32 #define MT6357_GPIO13_DIR_INPUT 0
35 #define MT6357_GPIO14_DIR_INPUT 0
38 #define MT6357_GPIO15_DIR_INPUT 0
42 #define MT6357_GPIO8_MODE_MASK GENMASK(2, 0)
43 #define MT6357_GPIO8_MODE_AUD_CLK_MOSI BIT(0)
44 #define MT6357_GPIO8_MODE_GPIO 0
47 #define MT6357_GPIO9_MODE_GPIO 0
50 #define MT6357_GPIO10_MODE_GPIO 0
53 #define MT6357_GPIO11_MODE_GPIO 0
56 #define MT6357_GPIO8_MODE_SET_MASK GENMASK(2, 0)
57 #define MT6357_GPIO8_MODE_SET_AUD_CLK_MOSI BIT(0)
66 #define MT6357_GPIO_MODE2_CLEAR_ALL GENMASK(15, 0)
69 #define MT6357_GPIO12_MODE_MASK GENMASK(2, 0)
70 #define MT6357_GPIO12_MODE_AUD_CLK_MISO BIT(0)
71 #define MT6357_GPIO12_MODE_GPIO 0
74 #define MT6357_GPIO13_MODE_GPIO 0
77 #define MT6357_GPIO14_MODE_GPIO 0
80 #define MT6357_GPIO15_MODE_GPIO 0
83 #define MT6357_GPIO12_MODE_SET_MASK GENMASK(2, 0)
84 #define MT6357_GPIO12_MODE_SET_AUD_CLK_MISO BIT(0)
93 #define MT6357_GPIO_MODE3_CLEAR_ALL GENMASK(15, 0)
99 #define MT6357_XO_AUDIO_EN_M_DISABLE 0
108 #define MT6357_DIVCKS_CHG BIT(0)
111 #define MT6357_DIVCKS_ON BIT(0)
114 #define MT6357_DIVCKS_PWD_NCP_MASK BIT(0)
115 #define MT6357_DIVCKS_PWD_NCP_DISABLE BIT(0)
116 #define MT6357_DIVCKS_PWD_NCP_ENABLE 0
119 #define MT6357_DIVCKS_PWD_NCP_ST_SEL_MASK GENMASK(1, 0)
120 #define MT6357_DIVCKS_PWD_NCP_ST_50US 0
127 #define MT6357_AFE_ON_SFT 0
130 #define MT6357_DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
135 #define MT6357_C_TWO_DIGITAL_MIC_DISABLE 0
140 #define MT6357_UL_SDM_3_LEVEL_DESELECT 0
141 #define MT6357_UL_SRC_ON_TMP_CTL_MASK BIT(0)
142 #define MT6357_UL_SRC_ENABLE BIT(0)
143 #define MT6357_UL_SRC_DISABLE 0
148 #define MT6357_DL_SINE_ON_SFT 0
149 #define MT6357_DL_SINE_ON_MASK BIT(0)
159 #define MT6357_PDN_RESERVED_SFT 0
163 #define MT6357_CCI_AUD_ANACK_NORMAL 0
166 #define MT6357_CCI_SCRAMBLER_CG_DISABLE 0
168 #define MT6357_CCI_LCK_INV_IN_PHASE 0
170 #define MT6357_CCI_RAND_DISABLE 0
172 #define MT6357_CCI_SPLT_SCRMB_CLK_OFF 0
174 #define MT6357_CCI_SPLT_SCRMB_OFF 0
176 #define MT6357_CCI_AUD_IDAC_TEST_EN_NORMAL_PATH 0
178 #define MT6357_CCI_ZERO_PADDING_ENABLE 0
180 #define MT6357_CCI_AUD_SPLIT_TEST_EN_NORMAL_PATH 0
182 #define MT6357_CCI_AUD_SDM_MUTE_L_NO_CTL 0
184 #define MT6357_CCI_AUD_SDM_MUTE_R_NO_CTL 0
186 #define MT6357_CCI_AUD_SDM_7BIT_FROM_SPLITTER1 0
187 #define MT6357_CCI_SCRAMBLER_ENABLE BIT(0)
188 #define MT6357_CCI_SCRAMBLER_DISABLE 0
192 #define MT6357_CCI_AUDIO_FIFO_DISABLE 0
194 #define MT6357_CCI_ACD_MODE_TEST_PATH 0
196 #define MT6357_CCI_AFIFO_CLK_PWDB_DOWN 0
197 #define MT6357_CCI_ACD_FUNC_RSTB_RELEASE BIT(0)
198 #define MT6357_CCI_ACD_FUNC_RSTB_RESET 0
203 #define MT6357_ADDA_MTKAIF_LPBK_DISABLE 0
209 #define MT6357_SGEN_MUTE_SW_DISABLE 0
218 #define MT6357_DCCLK_OUTPUT 0
219 #define MT6357_DCCLK_GEN_ON_MASK BIT(0)
220 #define MT6357_DCCLK_GEN_ON BIT(0)
221 #define MT6357_DCCLK_GEN_OFF 0
231 #define MT6357_AUD_PAD_TX_FIFO_LPBK_MASK GENMASK(7, 0)
232 #define MT6357_AUD_PAD_TX_FIFO_LPBK_ENABLE (BIT(5) | BIT(4) | BIT(0))
233 #define MT6357_AUD_PAD_TX_FIFO_LPBK_DISABLE 0
238 #define MT6357_AUDADCLINPUTSEL_IDLE 0
242 #define MT6357_AUDADCLPWRDOWN 0
247 #define MT6357_AUDPREAMPLINPUTSEL_MASK_NOSFT GENMASK(1, 0)
250 #define MT6357_AUDPREAMPLDCPRECHARGE_DISABLE 0
253 #define MT6357_AUDPREAMPLDCCEN_AC 0
254 #define MT6357_AUDPREAMPLON_MASK BIT(0)
255 #define MT6357_AUDPREAMPLON_ENABLE BIT(0)
256 #define MT6357_AUDPREAMPLON_DISABLE 0
261 #define MT6357_AUDADCRINPUTSEL_IDLE 0
265 #define MT6357_AUDADCRPWRDOWN 0
270 #define MT6357_AUDPREAMPRINPUTSEL_MASK_NOSFT GENMASK(1, 0)
273 #define MT6357_AUDPREAMPRDCPRECHARGE_DISABLE 0
276 #define MT6357_AUDPREAMPRDCCEN_AC 0
277 #define MT6357_AUDPREAMPRON_MASK BIT(0)
278 #define MT6357_AUDPREAMPRON_ENABLE BIT(0)
279 #define MT6357_AUDPREAMPRON_DISABLE 0
282 #define MT6357_CLKSQ_EN_SFT 0
287 #define MT6357_AUDDIGMICBIAS_OFF 0
288 #define MT6357_AUDDIGMICEN_MASK BIT(0)
289 #define MT6357_AUDDIGMICEN_ENABLE BIT(0)
290 #define MT6357_AUDDIGMICEN_DISABLE 0
295 #define MT6357_AUD_MICBIAS0_DCSW2N_DISABLE 0
298 #define MT6357_AUD_MICBIAS0_DCSW2P2_DISABLE 0
301 #define MT6357_AUD_MICBIAS0_DCSW2P1_DISABLE 0
304 #define MT6357_AUD_MICBIAS0_DCSWN_DISABLE 0
307 #define MT6357_AUD_MICBIAS0_DCSW0P2_DISABLE 0
310 #define MT6357_AUD_MICBIAS0_DCSW0P1_DISABLE 0
313 #define MT6357_AUD_MICBIAS0_PWD_SFT 0
332 #define MT6357_AUD_MICBIAS0_DC_DISABLE_ALL 0
337 #define MT6357_AUD_MICBIAS1_DCSW1P_DISABLE 0
340 #define MT6357_AUD_MICBIAS1_PWD_SFT 0
345 #define MT6357_AUD_HPR_SC_VAUDP15_ENABLE 0
348 #define MT6357_AUD_HPL_SC_VAUDP15_ENABLE 0
349 #define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
351 #define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
355 #define MT6357_AUD_HPR_BIAS_VAUDP15_DISABLE 0
358 #define MT6357_AUD_HPL_BIAS_VAUDP15_DISABLE 0
361 #define MT6357_AUD_HPR_PWRUP_VAUDP15_DISABLE 0
364 #define MT6357_AUD_HPL_PWRUP_VAUDP15_DISABLE 0
367 #define MT6357_AUD_DACL_PWRUP_VA28_DISABLE 0
370 #define MT6357_AUD_DACR_PWRUP_VA28_DISABLE 0
373 #define MT6357_AUD_DACR_PWRUP_VAUDP15_DISABLE 0
374 #define MT6357_AUD_DACL_PWRUP_VAUDP15_MASK BIT(0)
375 #define MT6357_AUD_DACL_PWRUP_VAUDP15_ENABLE BIT(0)
376 #define MT6357_AUD_DACL_PWRUP_VAUDP15_DISABLE 0
386 #define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_DISABLE 0
389 #define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_DISABLE 0
392 #define MT6357_HPR_AUX_FBRSW_VAUDP15_DISABLE 0
395 #define MT6357_HPL_AUX_FBRSW_VAUDP15_DISABLE 0
398 #define MT6357_HPROUT_AUX_PWRUP_VAUDP15_DISABLE 0
401 #define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_DISABLE 0
404 #define MT6357_HPROUT_PWRUP_VAUDP15_DISABLE 0
405 #define MT6357_HPLOUT_PWRUP_VAUDP15_MASK BIT(0)
406 #define MT6357_HPLOUT_PWRUP_VAUDP15_ENABLE BIT(0)
407 #define MT6357_HPLOUT_PWRUP_VAUDP15_DISABLE 0
412 #define MT6357_HPP_SHORT_2VCM_VAUDP15_DISABLE 0
415 #define MT6357_AUD_REFN_DERES_VAUDP15_DISABLE 0
417 #define MT6357_HPROUT_STB_ENH_VAUDP15_OPEN 0
423 #define MT6357_HPLOUT_STB_ENH_VAUDP15_MASK GENMASK(2, 0)
424 #define MT6357_HPLOUT_STB_ENH_VAUDP15_OPEN 0
425 #define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P250 BIT(0)
427 #define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P250 (BIT(0) | BIT(1))
428 #define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P470 (BIT(0) | BIT(2))
429 #define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P470 (BIT(0) | BIT(1) | BIT(2))
434 #define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_DISABLE 0
437 #define MT6357_AUD_HS_SC_VAUDP15_ENABLE 0
438 #define MT6357_AUD_HS_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
442 #define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_DISABLE 0
443 #define MT6357_AUD_HS_PWRUP_VAUDP15_MASK BIT(0)
444 #define MT6357_AUD_HS_PWRUP_VAUDP15_ENABLE BIT(0)
445 #define MT6357_AUD_HS_PWRUP_VAUDP15_DISABLE 0
450 #define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_DISABLE 0
453 #define MT6357_AUD_LOL_SC_VAUDP15_ENABLE 0
454 #define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
458 #define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_DISABLE 0
459 #define MT6357_AUD_LOL_PWRUP_VAUDP15_MASK BIT(0)
460 #define MT6357_AUD_LOL_PWRUP_VAUDP15_ENABLE BIT(0)
461 #define MT6357_AUD_LOL_PWRUP_VAUDP15_DISABLE 0
466 #define MT6357_HP_AUX_LOOP_GAIN_MAX 0x0f
469 #define MT6357_HPR_AUX_CMFB_LOOP_DISABLE 0
472 #define MT6357_HPL_AUX_CMFB_LOOP_DISABLE 0
475 #define MT6357_HPRL_MAIN_CMFB_LOOP_DISABLE 0
478 #define MT6357_HP_CMFB_RST_RESET 0
479 #define MT6357_DAC_LOW_NOISE_MODE_MASK BIT(0)
480 #define MT6357_DAC_LOW_NOISE_MODE_ENABLE BIT(0)
481 #define MT6357_DAC_LOW_NOISE_MODE_DISABLE 0
490 #define MT6357_AUD_IBIAS_PWRDN_VAUDP15_ENABLE 0
495 #define MT6357_RSTB_ENCODER_VA28_DISABLE 0
497 #define MT6357_RSTB_DECODER_VA28_MASK BIT(0)
498 #define MT6357_RSTB_DECODER_VA28_ENABLE BIT(0)
499 #define MT6357_RSTB_DECODER_VA28_DISABLE 0
504 #define MT6357_VA28REFGEN_EN_VA28_DISABLE 0
507 #define MT6357_VA33REFGEN_EN_VA18_DISABLE 0
510 #define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_DISABLE 0
513 #define MT6357_LCLDO_ENC_EN_VA28_DISABLE 0
516 #define MT6357_LCLDO_REMOTE_SENSE_VA18_DISABLE 0
519 #define MT6357_LCLDO_EN_VA18_DISABLE 0
522 #define MT6357_HCLDO_REMOTE_SENSE_VA18_DISABLE 0
523 #define MT6357_HCLDO_EN_VA18_MASK BIT(0)
524 #define MT6357_HCLDO_EN_VA18_ENABLE BIT(0)
525 #define MT6357_HCLDO_EN_VA18_DISABLE 0
528 #define MT6357_NVREG_EN_VAUDP15_MASK BIT(0)
529 #define MT6357_NVREG_EN_VAUDP15_ENABLE BIT(0)
530 #define MT6357_NVREG_EN_VAUDP15_DISABLE 0
535 #define MT6357_AUD_HP_TRIM_EN_VAUDP15_DISABLE 0
538 #define MT6357_AUD_LOL_GAIN_MASK GENMASK(4, 0)
539 #define MT6357_AUD_LOL_GAIN_SFT 0
542 #define MT6357_AUD_LO_GAIN_MAX 0x12
545 #define MT6357_AUD_HPL_GAIN_MASK GENMASK(4, 0)
546 #define MT6357_AUD_HPL_GAIN_SFT 0
549 #define MT6357_AUD_HP_GAIN_MAX 0x12
552 #define MT6357_AUD_HS_GAIN_MASK GENMASK(4, 0)
553 #define MT6357_AUD_HS_GAIN_SFT 0
554 #define MT6357_AUD_HS_GAIN_MAX 0x12
558 #define MT6357_GPIO_DIR0 0x0088
560 #define MT6357_GPIO_MODE2 0x00B6
561 #define MT6357_GPIO_MODE2_SET 0x00B8
562 #define MT6357_GPIO_MODE2_CLR 0x00BA
564 #define MT6357_GPIO_MODE3 0x00BC
565 #define MT6357_GPIO_MODE3_SET 0x00BE
566 #define MT6357_GPIO_MODE3_CLR 0x00C0
568 #define MT6357_DCXO_CW14 0x07AC
570 #define MT6357_AUD_TOP_CKPDN_CON0 0x208C
571 #define MT6357_AUDNCP_CLKDIV_CON0 0x20B4
572 #define MT6357_AUDNCP_CLKDIV_CON1 0x20B6
573 #define MT6357_AUDNCP_CLKDIV_CON2 0x20B8
574 #define MT6357_AUDNCP_CLKDIV_CON3 0x20BA
575 #define MT6357_AUDNCP_CLKDIV_CON4 0x20BC
576 #define MT6357_AFE_UL_DL_CON0 0x2108
577 #define MT6357_AFE_DL_SRC2_CON0_L 0x210A
578 #define MT6357_AFE_UL_SRC_CON0_H 0x210C
579 #define MT6357_AFE_UL_SRC_CON0_L 0x210E
580 #define MT6357_AFE_TOP_CON0 0x2110
581 #define MT6357_AUDIO_TOP_CON0 0x2112
582 #define MT6357_AFUNC_AUD_CON0 0x2116
583 #define MT6357_AFUNC_AUD_CON2 0x211A
584 #define MT6357_AFE_ADDA_MTKAIF_CFG0 0x2134
585 #define MT6357_AFE_SGEN_CFG0 0x2140
586 #define MT6357_AFE_DCCLK_CFG0 0x2146
587 #define MT6357_AFE_DCCLK_CFG1 0x2148
588 #define MT6357_AFE_AUD_PAD_TOP 0x214C
589 #define MT6357_AUDENC_ANA_CON0 0x2188
590 #define MT6357_AUDENC_ANA_CON1 0x218A
591 #define MT6357_AUDENC_ANA_CON6 0x2194
592 #define MT6357_AUDENC_ANA_CON7 0x2196
593 #define MT6357_AUDENC_ANA_CON8 0x2198
594 #define MT6357_AUDENC_ANA_CON9 0x219A
595 #define MT6357_AUDDEC_ANA_CON0 0x2208
596 #define MT6357_AUDDEC_ANA_CON1 0x220A
597 #define MT6357_AUDDEC_ANA_CON2 0x220C
598 #define MT6357_AUDDEC_ANA_CON3 0x220E
599 #define MT6357_AUDDEC_ANA_CON4 0x2210
600 #define MT6357_AUDDEC_ANA_CON6 0x2214
601 #define MT6357_AUDDEC_ANA_CON7 0x2216
602 #define MT6357_AUDDEC_ANA_CON10 0x221C
603 #define MT6357_AUDDEC_ANA_CON11 0x221E
604 #define MT6357_AUDDEC_ANA_CON12 0x2220
605 #define MT6357_AUDDEC_ANA_CON13 0x2222
606 #define MT6357_AUDDEC_ELR_0 0x2226
607 #define MT6357_ZCD_CON1 0x228A
608 #define MT6357_ZCD_CON2 0x228C
609 #define MT6357_ZCD_CON3 0x228E
612 DL_GAIN_8DB = 0,
617 DL_GAIN_N_40DB = 0x1f,
621 UL_GAIN_0DB = 0,
629 #define MT6357_DL_GAIN_REG_LEFT_MASK 0x001f
630 #define MT6357_DL_GAIN_REG_LEFT_SHIFT 0
631 #define MT6357_DL_GAIN_REG_RIGHT_MASK 0x0f80
633 #define MT6357_DL_GAIN_REG_MASK 0x0f9f