Lines Matching +full:0 +full:xf005
19 #define CDC_D_REVISION1 (0xf000)
20 #define CDC_D_PERPH_SUBTYPE (0xf005)
21 #define CDC_D_INT_EN_SET (0xf015)
22 #define CDC_D_INT_EN_CLR (0xf016)
27 #define CDC_D_CDC_RST_CTL (0xf046)
29 #define RST_CTL_DIG_SW_RST_N_RESET 0
32 #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
37 #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
38 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
45 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
46 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
57 #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
58 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
59 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
60 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
61 #define CONN_TX1_SERIAL_TX1_ZERO 0x2
63 #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
64 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
65 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
66 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
67 #define CONN_TX2_SERIAL_TX2_ZERO 0x2
68 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
69 #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
70 #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
71 #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
72 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
73 #define CDC_D_SEC_ACCESS (0xf0D0)
74 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
75 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
76 #define CDC_A_REVISION1 (0xf100)
77 #define CDC_A_REVISION2 (0xf101)
78 #define CDC_A_REVISION3 (0xf102)
79 #define CDC_A_REVISION4 (0xf103)
80 #define CDC_A_PERPH_TYPE (0xf104)
81 #define CDC_A_PERPH_SUBTYPE (0xf105)
82 #define CDC_A_INT_RT_STS (0xf110)
83 #define CDC_A_INT_SET_TYPE (0xf111)
84 #define CDC_A_INT_POLARITY_HIGH (0xf112)
85 #define CDC_A_INT_POLARITY_LOW (0xf113)
86 #define CDC_A_INT_LATCHED_CLR (0xf114)
87 #define CDC_A_INT_EN_SET (0xf115)
88 #define CDC_A_INT_EN_CLR (0xf116)
89 #define CDC_A_INT_LATCHED_STS (0xf118)
90 #define CDC_A_INT_PENDING_STS (0xf119)
91 #define CDC_A_INT_MID_SEL (0xf11A)
92 #define CDC_A_INT_PRIORITY (0xf11B)
93 #define CDC_A_MICB_1_EN (0xf140)
97 #define MICB_1_EN_EXT_BYP_CAP 0
101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
103 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
104 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
106 #define CDC_A_MICB_1_VAL (0xf141)
111 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
112 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
113 #define CDC_A_MICB_1_CTL (0xf142)
122 #define CDC_A_MICB_1_INT_RBIAS (0xf143)
125 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
133 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
140 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
141 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
142 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
145 #define CDC_A_MICB_2_EN (0xf144)
149 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
150 #define CDC_A_MASTER_BIAS_CTL (0xf146)
151 #define CDC_A_MBHC_DET_CTL_1 (0xf147)
155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
162 #define CDC_A_MBHC_DET_CTL_2 (0xf150)
168 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
170 #define CDC_A_MBHC_FSM_CTL (0xf151)
173 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
175 #define CDC_A_MBHC_DBNC_TIMER (0xf152)
177 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
178 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
179 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
180 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
181 #define CDC_A_MBHC_BTN3_CTL (0xf156)
182 #define CDC_A_MBHC_BTN4_CTL (0xf157)
189 #define CDC_A_MBHC_RESULT_1 (0xf158)
190 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
191 #define CDC_A_TX_1_EN (0xf160)
192 #define CDC_A_TX_2_EN (0xf161)
193 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
194 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
195 #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
196 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
197 #define CDC_A_TX_3_EN (0xf167)
198 #define CDC_A_NCP_EN (0xf180)
199 #define CDC_A_NCP_CLK (0xf181)
200 #define CDC_A_NCP_FBCTRL (0xf183)
203 #define CDC_A_NCP_BIAS (0xf184)
204 #define CDC_A_NCP_VCTRL (0xf185)
205 #define CDC_A_NCP_TEST (0xf186)
206 #define CDC_A_NCP_CLIM_ADDR (0xf187)
207 #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
208 #define CDC_A_RX_COM_OCP_CTL (0xf191)
209 #define CDC_A_RX_COM_OCP_COUNT (0xf192)
210 #define CDC_A_RX_COM_BIAS_DAC (0xf193)
213 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
214 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
216 #define CDC_A_RX_HPH_BIAS_PA (0xf194)
217 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
218 #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
219 #define CDC_A_RX_HPH_CNP_EN (0xf197)
220 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
223 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
227 #define CDC_A_RX_EAR_CTL (0xf19E)
228 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
235 #define CDC_A_SPKR_DAC_CTL (0xf1B0)
237 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
239 #define CDC_A_SPKR_DRV_CTL (0xf1B2)
240 #define SPKR_DRV_CTL_DEF_MASK 0xEF
248 #define SPKR_DRV_GAIN_SET BIT(0)
253 #define CDC_A_SPKR_OCP_CTL (0xf1B4)
254 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
255 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
256 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
257 #define SPKR_PWRSTG_CTL_MASK 0xE0
265 #define CDC_A_SPKR_DRV_DBG (0xf1B7)
266 #define CDC_A_CURRENT_LIMIT (0xf1C0)
267 #define CDC_A_BOOST_EN_CTL (0xf1C3)
268 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
269 #define CDC_A_SEC_ACCESS (0xf1D0)
270 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
271 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
328 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
331 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
339 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
340 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
343 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
344 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
345 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
372 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); in pm8916_wcd_analog_micbias_enable()
387 return 0; in pm8916_wcd_analog_enable_micbias()
404 return 0; in pm8916_wcd_analog_enable_micbias_int()
445 0); in pm8916_mbhc_configure_bias()
456 vrefs = &priv->vref_btn_micb[0]; in pm8916_mbhc_configure_bias()
458 vrefs = &priv->vref_btn_cs[0]; in pm8916_mbhc_configure_bias()
462 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { in pm8916_mbhc_configure_bias()
474 return 0; in pm8916_mbhc_configure_bias()
481 u32 plug_type = 0; in pm8916_wcd_setup_mbhc()
521 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); in pm8916_wcd_setup_mbhc()
538 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 0); in pm8916_wcd_analog_enable_micbias_int2()
598 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); in pm8916_wcd_analog_enable_adc()
609 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); in pm8916_wcd_analog_enable_adc()
621 return 0; in pm8916_wcd_analog_enable_adc()
659 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); in pm8916_wcd_analog_enable_spk_pa()
665 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); in pm8916_wcd_analog_enable_spk_pa()
668 return 0; in pm8916_wcd_analog_enable_spk_pa()
689 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0); in pm8916_wcd_analog_enable_ear_pa()
693 RX_EAR_CTL_PA_SEL_MASK, 0); in pm8916_wcd_analog_enable_ear_pa()
696 return 0; in pm8916_wcd_analog_enable_ear_pa()
700 {CDC_A_RX_COM_OCP_CTL, 0xD1},
701 {CDC_A_RX_COM_OCP_COUNT, 0xFF},
702 {CDC_D_SEC_ACCESS, 0xA5},
703 {CDC_D_PERPH_RESET_CTL3, 0x0F},
704 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
705 {CDC_A_NCP_FBCTRL, 0x28},
706 {CDC_A_SPKR_DRV_CTL, 0x69},
707 {CDC_A_SPKR_DRV_DBG, 0x01},
708 {CDC_A_BOOST_EN_CTL, 0x5F},
709 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
710 {CDC_A_SEC_ACCESS, 0xA5},
711 {CDC_A_PERPH_RESET_CTL3, 0x0F},
712 {CDC_A_CURRENT_LIMIT, 0x82},
713 {CDC_A_SPKR_DAC_CTL, 0x03},
714 {CDC_A_SPKR_OCP_CTL, 0xE1},
715 {CDC_A_MASTER_BIAS_CTL, 0x30},
724 if (err != 0) { in pm8916_wcd_analog_probe()
738 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); in pm8916_wcd_analog_probe()
739 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); in pm8916_wcd_analog_probe()
741 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) in pm8916_wcd_analog_probe()
753 return 0; in pm8916_wcd_analog_probe()
761 RST_CTL_DIG_SW_RST_N_MASK, 0); in pm8916_wcd_analog_remove()
863 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
864 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
865 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
866 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
876 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
879 0, 0, NULL, 0,
883 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux),
884 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0),
886 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
887 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
888 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
889 0),
890 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
891 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
892 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
893 0),
894 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
900 6, 0, NULL, 0,
904 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
905 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
907 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
908 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
911 SND_SOC_DAPM_SUPPLY("MIC_BIAS1", CDC_A_MICB_1_EN, 7, 0,
914 SND_SOC_DAPM_SUPPLY("MIC_BIAS2", CDC_A_MICB_2_EN, 7, 0,
918 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", SND_SOC_NOPM, 0, 0, NULL, 0),
919 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", SND_SOC_NOPM, 0, 0, NULL, 0),
921 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_INT_RBIAS, 7, 0,
924 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_1_INT_RBIAS, 4, 0,
928 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3", CDC_A_MICB_1_INT_RBIAS, 1, 0,
932 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
936 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
940 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
945 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
946 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
948 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
949 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
952 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
953 0),
954 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
955 0),
956 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
957 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
961 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
962 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
963 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
965 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
966 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
967 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
968 0),
971 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
973 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
984 return 0; in pm8916_wcd_analog_set_jack()
1000 snd_soc_jack_report(priv->jack, 0, btn_mask); in mbhc_btn_release_irq_handler()
1016 case 0xf: in mbhc_btn_press_irq_handler()
1019 case 0x7: in mbhc_btn_press_irq_handler()
1022 case 0x3: in mbhc_btn_press_irq_handler()
1025 case 0x1: in mbhc_btn_press_irq_handler()
1028 case 0x0: in mbhc_btn_press_irq_handler()
1084 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); in pm8916_mbhc_switch_irq_handler()
1093 [0] = {
1095 .id = 0,
1165 &priv->vref_btn_cs[0], in pm8916_wcd_analog_parse_dt()
1167 if (rval < 0) { in pm8916_wcd_analog_parse_dt()
1172 &priv->vref_btn_micb[0], in pm8916_wcd_analog_parse_dt()
1174 if (rval < 0) in pm8916_wcd_analog_parse_dt()
1183 return 0; in pm8916_wcd_analog_parse_dt()
1197 if (ret < 0) in pm8916_wcd_analog_spmi_probe()
1200 for (i = 0; i < ARRAY_SIZE(supply_names); i++) in pm8916_wcd_analog_spmi_probe()
1211 if (irq < 0) in pm8916_wcd_analog_spmi_probe()
1226 if (irq < 0) in pm8916_wcd_analog_spmi_probe()
1240 if (irq < 0) in pm8916_wcd_analog_spmi_probe()