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1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
101 #define M98090_REG_CNT (0xFF+1)
109 #define M98090_SWRESET_MASK (1<<7)
111 #define M98090_SWRESET_WIDTH 1
116 #define M98090_CLD_MASK (1<<7)
118 #define M98090_CLD_WIDTH 1
119 #define M98090_SLD_MASK (1<<6)
121 #define M98090_SLD_WIDTH 1
122 #define M98090_ULK_MASK (1<<5)
124 #define M98090_ULK_WIDTH 1
125 #define M98090_JDET_MASK (1<<2)
127 #define M98090_JDET_WIDTH 1
128 #define M98090_DRCACT_MASK (1<<1)
129 #define M98090_DRCACT_SHIFT 1
130 #define M98090_DRCACT_WIDTH 1
131 #define M98090_DRCCLP_MASK (1<<0)
133 #define M98090_DRCCLP_WIDTH 1
138 #define M98090_LSNS_MASK (1<<2)
140 #define M98090_LSNS_WIDTH 1
141 #define M98090_JKSNS_MASK (1<<1)
142 #define M98090_JKSNS_SHIFT 1
143 #define M98090_JKSNS_WIDTH 1
148 #define M98090_ICLD_MASK (1<<7)
150 #define M98090_ICLD_WIDTH 1
151 #define M98090_ISLD_MASK (1<<6)
153 #define M98090_ISLD_WIDTH 1
154 #define M98090_IULK_MASK (1<<5)
156 #define M98090_IULK_WIDTH 1
157 #define M98090_IJDET_MASK (1<<2)
159 #define M98090_IJDET_WIDTH 1
160 #define M98090_IDRCACT_MASK (1<<1)
161 #define M98090_IDRCACT_SHIFT 1
162 #define M98090_IDRCACT_WIDTH 1
163 #define M98090_IDRCCLP_MASK (1<<0)
165 #define M98090_IDRCCLP_WIDTH 1
170 #define M98090_26M_MASK (1<<7)
172 #define M98090_26M_WIDTH 1
173 #define M98090_19P2M_MASK (1<<6)
175 #define M98090_19P2M_WIDTH 1
176 #define M98090_13M_MASK (1<<5)
178 #define M98090_13M_WIDTH 1
179 #define M98090_12P288M_MASK (1<<4)
181 #define M98090_12P288M_WIDTH 1
182 #define M98090_12M_MASK (1<<3)
184 #define M98090_12M_WIDTH 1
185 #define M98090_11P2896M_MASK (1<<2)
187 #define M98090_11P2896M_WIDTH 1
188 #define M98090_256FS_MASK (1<<0)
190 #define M98090_256FS_WIDTH 1
193 #define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
198 #define M98090_SR_96K_MASK (1<<5)
200 #define M98090_SR_96K_WIDTH 1
201 #define M98090_SR_32K_MASK (1<<4)
203 #define M98090_SR_32K_WIDTH 1
204 #define M98090_SR_48K_MASK (1<<3)
206 #define M98090_SR_48K_WIDTH 1
207 #define M98090_SR_44K1_MASK (1<<2)
209 #define M98090_SR_44K1_WIDTH 1
210 #define M98090_SR_16K_MASK (1<<1)
211 #define M98090_SR_16K_SHIFT 1
212 #define M98090_SR_16K_WIDTH 1
213 #define M98090_SR_8K_MASK (1<<0)
215 #define M98090_SR_8K_WIDTH 1
219 #define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
224 #define M98090_RJ_M_MASK (1<<5)
226 #define M98090_RJ_M_WIDTH 1
227 #define M98090_RJ_S_MASK (1<<4)
229 #define M98090_RJ_S_WIDTH 1
230 #define M98090_LJ_M_MASK (1<<3)
232 #define M98090_LJ_M_WIDTH 1
233 #define M98090_LJ_S_MASK (1<<2)
235 #define M98090_LJ_S_WIDTH 1
236 #define M98090_I2S_M_MASK (1<<1)
237 #define M98090_I2S_M_SHIFT 1
238 #define M98090_I2S_M_WIDTH 1
239 #define M98090_I2S_S_MASK (1<<0)
241 #define M98090_I2S_S_WIDTH 1
244 #define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
249 #define M98090_DIG2_HP_MASK (1<<7)
251 #define M98090_DIG2_HP_WIDTH 1
252 #define M98090_DIG2_EAR_MASK (1<<6)
254 #define M98090_DIG2_EAR_WIDTH 1
255 #define M98090_DIG2_SPK_MASK (1<<5)
257 #define M98090_DIG2_SPK_WIDTH 1
258 #define M98090_DIG2_LOUT_MASK (1<<4)
260 #define M98090_DIG2_LOUT_WIDTH 1
263 #define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
268 #define M98090_IN12_MIC1_MASK (1<<7)
270 #define M98090_IN12_MIC1_WIDTH 1
271 #define M98090_IN34_MIC2_MASK (1<<6)
273 #define M98090_IN34_MIC2_WIDTH 1
274 #define M98090_IN56_MIC1_MASK (1<<5)
276 #define M98090_IN56_MIC1_WIDTH 1
277 #define M98090_IN56_MIC2_MASK (1<<4)
279 #define M98090_IN56_MIC2_WIDTH 1
280 #define M98090_IN12_DADC_MASK (1<<3)
282 #define M98090_IN12_DADC_WIDTH 1
283 #define M98090_IN34_DADC_MASK (1<<2)
285 #define M98090_IN34_DADC_WIDTH 1
286 #define M98090_IN56_DADC_MASK (1<<1)
287 #define M98090_IN56_DADC_SHIFT 1
288 #define M98090_IN56_DADC_WIDTH 1
291 #define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
296 #define M98090_IN12S_AB_MASK (1<<7)
298 #define M98090_IN12S_AB_WIDTH 1
299 #define M98090_IN34S_AB_MASK (1<<6)
301 #define M98090_IN34S_AB_WIDTH 1
302 #define M98090_IN56S_AB_MASK (1<<5)
304 #define M98090_IN56S_AB_WIDTH 1
305 #define M98090_IN34D_A_MASK (1<<4)
307 #define M98090_IN34D_A_WIDTH 1
308 #define M98090_IN56D_B_MASK (1<<3)
310 #define M98090_IN56D_B_WIDTH 1
313 #define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
318 #define M98090_IN12_M1HPL_MASK (1<<7)
320 #define M98090_IN12_M1HPL_WIDTH 1
321 #define M98090_IN12_M1SPKL_MASK (1<<6)
323 #define M98090_IN12_M1SPKL_WIDTH 1
324 #define M98090_IN12_M1EAR_MASK (1<<5)
326 #define M98090_IN12_M1EAR_WIDTH 1
327 #define M98090_IN12_M1LOUTL_MASK (1<<4)
329 #define M98090_IN12_M1LOUTL_WIDTH 1
330 #define M98090_IN34_M2HPR_MASK (1<<3)
332 #define M98090_IN34_M2HPR_WIDTH 1
333 #define M98090_IN34_M2SPKR_MASK (1<<2)
335 #define M98090_IN34_M2SPKR_WIDTH 1
336 #define M98090_IN34_M2EAR_MASK (1<<1)
337 #define M98090_IN34_M2EAR_SHIFT 1
338 #define M98090_IN34_M2EAR_WIDTH 1
339 #define M98090_IN34_M2LOUTR_MASK (1<<0)
341 #define M98090_IN34_M2LOUTR_WIDTH 1
344 #define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
349 #define M98090_IN12S_ABHP_MASK (1<<7)
351 #define M98090_IN12S_ABHP_WIDTH 1
352 #define M98090_IN34D_ASPKL_MASK (1<<6)
354 #define M98090_IN34D_ASPKL_WIDTH 1
355 #define M98090_IN34D_AEAR_MASK (1<<5)
357 #define M98090_IN34D_AEAR_WIDTH 1
358 #define M98090_IN12S_ABLOUT_MASK (1<<4)
360 #define M98090_IN12S_ABLOUT_WIDTH 1
361 #define M98090_IN34S_ABHP_MASK (1<<3)
363 #define M98090_IN34S_ABHP_WIDTH 1
364 #define M98090_IN56D_BSPKR_MASK (1<<2)
366 #define M98090_IN56D_BSPKR_WIDTH 1
367 #define M98090_IN56D_BEAR_MASK (1<<1)
368 #define M98090_IN56D_BEAR_SHIFT 1
369 #define M98090_IN56D_BEAR_WIDTH 1
370 #define M98090_IN34S_ABLOUT_MASK (1<<0)
372 #define M98090_IN34S_ABLOUT_WIDTH 1
375 #define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
384 #define M98090_IN34DIFF_MASK (1<<7)
386 #define M98090_IN34DIFF_WIDTH 1
387 #define M98090_IN56DIFF_MASK (1<<6)
389 #define M98090_IN56DIFF_WIDTH 1
390 #define M98090_IN1SEEN_MASK (1<<5)
392 #define M98090_IN1SEEN_WIDTH 1
393 #define M98090_IN2SEEN_MASK (1<<4)
395 #define M98090_IN2SEEN_WIDTH 1
396 #define M98090_IN3SEEN_MASK (1<<3)
398 #define M98090_IN3SEEN_WIDTH 1
399 #define M98090_IN4SEEN_MASK (1<<2)
401 #define M98090_IN4SEEN_WIDTH 1
402 #define M98090_IN5SEEN_MASK (1<<1)
403 #define M98090_IN5SEEN_SHIFT 1
404 #define M98090_IN5SEEN_WIDTH 1
405 #define M98090_IN6SEEN_MASK (1<<0)
407 #define M98090_IN6SEEN_WIDTH 1
412 #define M98090_MIXG135_MASK (1<<7)
414 #define M98090_MIXG135_WIDTH 1
415 #define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
416 #define M98090_MIXG246_MASK (1<<6)
418 #define M98090_MIXG246_WIDTH 1
419 #define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
432 #define M98090_EXTBUFA_MASK (1<<7)
434 #define M98090_EXTBUFA_WIDTH 1
435 #define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
436 #define M98090_EXTBUFB_MASK (1<<6)
438 #define M98090_EXTBUFB_WIDTH 1
439 #define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
443 #define M98090_EXTMIC2_SHIFT 1
446 #define M98090_EXTMIC_MIC1 (1<<0)
481 #define M98090_MBVSEL_2V4 (1<<0)
490 #define M98090_DIGMIC4_MASK (1<<3)
492 #define M98090_DIGMIC4_WIDTH 1
493 #define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
494 #define M98090_DIGMIC3_MASK (1<<2)
496 #define M98090_DIGMIC3_WIDTH 1
497 #define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
498 #define M98090_DIGMICR_MASK (1<<1)
499 #define M98090_DIGMICR_SHIFT 1
500 #define M98090_DIGMICR_WIDTH 1
501 #define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
502 #define M98090_DIGMICL_MASK (1<<0)
504 #define M98090_DIGMICL_WIDTH 1
505 #define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
513 #define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
521 #define M98090_MIXADL_MIC2_MASK (1<<6)
523 #define M98090_MIXADL_MIC2_WIDTH 1
524 #define M98090_MIXADL_MIC1_MASK (1<<5)
526 #define M98090_MIXADL_MIC1_WIDTH 1
527 #define M98090_MIXADL_LINEB_MASK (1<<4)
529 #define M98090_MIXADL_LINEB_WIDTH 1
530 #define M98090_MIXADL_LINEA_MASK (1<<3)
532 #define M98090_MIXADL_LINEA_WIDTH 1
533 #define M98090_MIXADL_IN65DIFF_MASK (1<<2)
535 #define M98090_MIXADL_IN65DIFF_WIDTH 1
536 #define M98090_MIXADL_IN34DIFF_MASK (1<<1)
537 #define M98090_MIXADL_IN34DIFF_SHIFT 1
538 #define M98090_MIXADL_IN34DIFF_WIDTH 1
539 #define M98090_MIXADL_IN12DIFF_MASK (1<<0)
541 #define M98090_MIXADL_IN12DIFF_WIDTH 1
542 #define M98090_MIXADL_MASK (255<<0)
549 #define M98090_MIXADR_MIC2_MASK (1<<6)
551 #define M98090_MIXADR_MIC2_WIDTH 1
552 #define M98090_MIXADR_MIC1_MASK (1<<5)
554 #define M98090_MIXADR_MIC1_WIDTH 1
555 #define M98090_MIXADR_LINEB_MASK (1<<4)
557 #define M98090_MIXADR_LINEB_WIDTH 1
558 #define M98090_MIXADR_LINEA_MASK (1<<3)
560 #define M98090_MIXADR_LINEA_WIDTH 1
561 #define M98090_MIXADR_IN65DIFF_MASK (1<<2)
563 #define M98090_MIXADR_IN65DIFF_WIDTH 1
564 #define M98090_MIXADR_IN34DIFF_MASK (1<<1)
565 #define M98090_MIXADR_IN34DIFF_SHIFT 1
566 #define M98090_MIXADR_IN34DIFF_WIDTH 1
567 #define M98090_MIXADR_IN12DIFF_MASK (1<<0)
569 #define M98090_MIXADR_IN12DIFF_WIDTH 1
570 #define M98090_MIXADR_MASK (255<<0)
580 #define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
584 #define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
592 #define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
596 #define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
604 #define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
609 #define M98090_DSTSR_MASK (1<<7)
611 #define M98090_DSTSR_WIDTH 1
612 #define M98090_DSTSL_MASK (1<<6)
614 #define M98090_DSTSL_WIDTH 1
627 #define M98090_PSCLK_DIV1 (1<<4)
637 #define M98090_USE_M1_MASK (1<<0)
639 #define M98090_USE_M1_WIDTH 1
640 #define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
648 #define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
653 #define M98090_NI_LO_MASK (255<<0)
656 #define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
661 #define M98090_MI_HI_MASK (255<<0)
664 #define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
669 #define M98090_MI_LO_MASK (255<<0)
672 #define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
677 #define M98090_MAS_MASK (1<<7)
679 #define M98090_MAS_WIDTH 1
680 #define M98090_BSEL_MASK (1<<0)
682 #define M98090_BSEL_WIDTH 1
683 #define M98090_BSEL_32 (1<<0)
690 #define M98090_RJ_MASK (1<<5)
692 #define M98090_RJ_WIDTH 1
693 #define M98090_WCI_MASK (1<<4)
695 #define M98090_WCI_WIDTH 1
696 #define M98090_BCI_MASK (1<<3)
698 #define M98090_BCI_WIDTH 1
699 #define M98090_DLY_MASK (1<<2)
701 #define M98090_DLY_WIDTH 1
705 #define M98090_WS_NUM (1<<M98090_WS_WIDTH)
710 #define M98090_FSW_MASK (1<<1)
711 #define M98090_FSW_SHIFT 1
712 #define M98090_FSW_WIDTH 1
713 #define M98090_TDM_MASK (1<<0)
715 #define M98090_TDM_WIDTH 1
716 #define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
724 #define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
728 #define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
732 #define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
737 #define M98090_LTEN_MASK (1<<5)
739 #define M98090_LTEN_WIDTH 1
740 #define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
741 #define M98090_LBEN_MASK (1<<4)
743 #define M98090_LBEN_WIDTH 1
744 #define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
745 #define M98090_DMONO_MASK (1<<3)
747 #define M98090_DMONO_WIDTH 1
748 #define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
749 #define M98090_HIZOFF_MASK (1<<2)
751 #define M98090_HIZOFF_WIDTH 1
752 #define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
753 #define M98090_SDOEN_MASK (1<<1)
754 #define M98090_SDOEN_SHIFT 1
755 #define M98090_SDOEN_WIDTH 1
756 #define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
757 #define M98090_SDIEN_MASK (1<<0)
759 #define M98090_SDIEN_WIDTH 1
760 #define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
765 #define M98090_MODE_MASK (1<<7)
767 #define M98090_MODE_WIDTH 1
768 #define M98090_AHPF_MASK (1<<6)
770 #define M98090_AHPF_WIDTH 1
771 #define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
772 #define M98090_DHPF_MASK (1<<5)
774 #define M98090_DHPF_WIDTH 1
775 #define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
776 #define M98090_DHF_MASK (1<<4)
778 #define M98090_DHF_WIDTH 1
779 #define M98090_FLT_DMIC34MODE_MASK (1<<3)
781 #define M98090_FLT_DMIC34MODE_WIDTH 1
782 #define M98090_FLT_DMIC34HPF_MASK (1<<2)
784 #define M98090_FLT_DMIC34HPF_WIDTH 1
785 #define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
790 #define M98090_DVM_MASK (1<<7)
792 #define M98090_DVM_WIDTH 1
796 #define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
800 #define M98090_DV_NUM (1<<M98090_DV_WIDTH)
805 #define M98090_EQCLPN_MASK (1<<4)
807 #define M98090_EQCLPN_WIDTH 1
808 #define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
812 #define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
817 #define M98090_MIXHPL_MIC2_MASK (1<<5)
819 #define M98090_MIXHPL_MIC2_WIDTH 1
820 #define M98090_MIXHPL_MIC1_MASK (1<<4)
822 #define M98090_MIXHPL_MIC1_WIDTH 1
823 #define M98090_MIXHPL_LINEB_MASK (1<<3)
825 #define M98090_MIXHPL_LINEB_WIDTH 1
826 #define M98090_MIXHPL_LINEA_MASK (1<<2)
828 #define M98090_MIXHPL_LINEA_WIDTH 1
829 #define M98090_MIXHPL_DACR_MASK (1<<1)
830 #define M98090_MIXHPL_DACR_SHIFT 1
831 #define M98090_MIXHPL_DACR_WIDTH 1
832 #define M98090_MIXHPL_DACL_MASK (1<<0)
834 #define M98090_MIXHPL_DACL_WIDTH 1
842 #define M98090_MIXHPR_MIC2_MASK (1<<5)
844 #define M98090_MIXHPR_MIC2_WIDTH 1
845 #define M98090_MIXHPR_MIC1_MASK (1<<4)
847 #define M98090_MIXHPR_MIC1_WIDTH 1
848 #define M98090_MIXHPR_LINEB_MASK (1<<3)
850 #define M98090_MIXHPR_LINEB_WIDTH 1
851 #define M98090_MIXHPR_LINEA_MASK (1<<2)
853 #define M98090_MIXHPR_LINEA_WIDTH 1
854 #define M98090_MIXHPR_DACR_MASK (1<<1)
855 #define M98090_MIXHPR_DACR_SHIFT 1
856 #define M98090_MIXHPR_DACR_WIDTH 1
857 #define M98090_MIXHPR_DACL_MASK (1<<0)
859 #define M98090_MIXHPR_DACL_WIDTH 1
867 #define M98090_MIXHPRSEL_MASK (1<<5)
869 #define M98090_MIXHPRSEL_WIDTH 1
870 #define M98090_MIXHPLSEL_MASK (1<<4)
872 #define M98090_MIXHPLSEL_WIDTH 1
876 #define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
880 #define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
885 #define M98090_HPLM_MASK (1<<7)
887 #define M98090_HPLM_WIDTH 1
891 #define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
896 #define M98090_HPRM_MASK (1<<7)
898 #define M98090_HPRM_WIDTH 1
902 #define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
907 #define M98090_MIXSPL_MIC2_MASK (1<<5)
909 #define M98090_MIXSPL_MIC2_WIDTH 1
910 #define M98090_MIXSPL_MIC1_MASK (1<<4)
912 #define M98090_MIXSPL_MIC1_WIDTH 1
913 #define M98090_MIXSPL_LINEB_MASK (1<<3)
915 #define M98090_MIXSPL_LINEB_WIDTH 1
916 #define M98090_MIXSPL_LINEA_MASK (1<<2)
918 #define M98090_MIXSPL_LINEA_WIDTH 1
919 #define M98090_MIXSPL_DACR_MASK (1<<1)
920 #define M98090_MIXSPL_DACR_SHIFT 1
921 #define M98090_MIXSPL_DACR_WIDTH 1
922 #define M98090_MIXSPL_DACL_MASK (1<<0)
924 #define M98090_MIXSPL_DACL_WIDTH 1
928 #define M98090_MIXSPR_DACR_MASK (1<<1)
929 #define M98090_MIXSPR_DACR_SHIFT 1
930 #define M98090_MIXSPR_DACR_WIDTH 1
936 #define M98090_SPK_SLAVE_MASK (1<<6)
938 #define M98090_SPK_SLAVE_WIDTH 1
939 #define M98090_MIXSPR_MIC2_MASK (1<<5)
941 #define M98090_MIXSPR_MIC2_WIDTH 1
942 #define M98090_MIXSPR_MIC1_MASK (1<<4)
944 #define M98090_MIXSPR_MIC1_WIDTH 1
945 #define M98090_MIXSPR_LINEB_MASK (1<<3)
947 #define M98090_MIXSPR_LINEB_WIDTH 1
948 #define M98090_MIXSPR_LINEA_MASK (1<<2)
950 #define M98090_MIXSPR_LINEA_WIDTH 1
951 #define M98090_MIXSPR_DACR_MASK (1<<1)
952 #define M98090_MIXSPR_DACR_SHIFT 1
953 #define M98090_MIXSPR_DACR_WIDTH 1
954 #define M98090_MIXSPR_DACL_MASK (1<<0)
956 #define M98090_MIXSPR_DACL_WIDTH 1
967 #define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
971 #define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
976 #define M98090_SPLM_MASK (1<<7)
978 #define M98090_SPLM_WIDTH 1
987 #define M98090_SPRM_MASK (1<<7)
989 #define M98090_SPRM_WIDTH 1
998 #define M98090_DRCEN_MASK (1<<7)
1000 #define M98090_DRCEN_WIDTH 1
1001 #define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
1018 #define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
1029 #define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
1042 #define M98090_MIXRCVL_MIC2_MASK (1<<5)
1044 #define M98090_MIXRCVL_MIC2_WIDTH 1
1045 #define M98090_MIXRCVL_MIC1_MASK (1<<4)
1047 #define M98090_MIXRCVL_MIC1_WIDTH 1
1048 #define M98090_MIXRCVL_LINEB_MASK (1<<3)
1050 #define M98090_MIXRCVL_LINEB_WIDTH 1
1051 #define M98090_MIXRCVL_LINEA_MASK (1<<2)
1053 #define M98090_MIXRCVL_LINEA_WIDTH 1
1054 #define M98090_MIXRCVL_DACR_MASK (1<<1)
1055 #define M98090_MIXRCVL_DACR_SHIFT 1
1056 #define M98090_MIXRCVL_DACR_WIDTH 1
1057 #define M98090_MIXRCVL_DACL_MASK (1<<0)
1059 #define M98090_MIXRCVL_DACL_WIDTH 1
1070 #define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
1075 #define M98090_RCVLM_MASK (1<<7)
1077 #define M98090_RCVLM_WIDTH 1
1081 #define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
1086 #define M98090_LINMOD_MASK (1<<7)
1088 #define M98090_LINMOD_WIDTH 1
1089 #define M98090_MIXRCVR_MIC2_MASK (1<<5)
1091 #define M98090_MIXRCVR_MIC2_WIDTH 1
1092 #define M98090_MIXRCVR_MIC1_MASK (1<<4)
1094 #define M98090_MIXRCVR_MIC1_WIDTH 1
1095 #define M98090_MIXRCVR_LINEB_MASK (1<<3)
1097 #define M98090_MIXRCVR_LINEB_WIDTH 1
1098 #define M98090_MIXRCVR_LINEA_MASK (1<<2)
1100 #define M98090_MIXRCVR_LINEA_WIDTH 1
1101 #define M98090_MIXRCVR_DACR_MASK (1<<1)
1102 #define M98090_MIXRCVR_DACR_SHIFT 1
1103 #define M98090_MIXRCVR_DACR_WIDTH 1
1104 #define M98090_MIXRCVR_DACL_MASK (1<<0)
1106 #define M98090_MIXRCVR_DACL_WIDTH 1
1117 #define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
1122 #define M98090_RCVRM_MASK (1<<7)
1124 #define M98090_RCVRM_WIDTH 1
1128 #define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
1133 #define M98090_JDETEN_MASK (1<<7)
1135 #define M98090_JDETEN_WIDTH 1
1136 #define M98090_JDWK_MASK (1<<6)
1138 #define M98090_JDWK_WIDTH 1
1143 #define M98090_JDEB_50MS (1<<0)
1150 #define M98090_MBEN_MASK (1<<4)
1152 #define M98090_MBEN_WIDTH 1
1153 #define M98090_LINEAEN_MASK (1<<3)
1155 #define M98090_LINEAEN_WIDTH 1
1156 #define M98090_LINEBEN_MASK (1<<2)
1158 #define M98090_LINEBEN_WIDTH 1
1159 #define M98090_ADREN_MASK (1<<1)
1160 #define M98090_ADREN_SHIFT 1
1161 #define M98090_ADREN_WIDTH 1
1162 #define M98090_ADLEN_MASK (1<<0)
1164 #define M98090_ADLEN_WIDTH 1
1169 #define M98090_HPREN_MASK (1<<7)
1171 #define M98090_HPREN_WIDTH 1
1172 #define M98090_HPLEN_MASK (1<<6)
1174 #define M98090_HPLEN_WIDTH 1
1175 #define M98090_SPREN_MASK (1<<5)
1177 #define M98090_SPREN_WIDTH 1
1178 #define M98090_SPLEN_MASK (1<<4)
1180 #define M98090_SPLEN_WIDTH 1
1181 #define M98090_RCVLEN_MASK (1<<3)
1183 #define M98090_RCVLEN_WIDTH 1
1184 #define M98090_RCVREN_MASK (1<<2)
1186 #define M98090_RCVREN_WIDTH 1
1187 #define M98090_DAREN_MASK (1<<1)
1188 #define M98090_DAREN_SHIFT 1
1189 #define M98090_DAREN_WIDTH 1
1190 #define M98090_DALEN_MASK (1<<0)
1192 #define M98090_DALEN_WIDTH 1
1197 #define M98090_ZDENN_MASK (1<<2)
1199 #define M98090_ZDENN_WIDTH 1
1200 #define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
1201 #define M98090_VS2ENN_MASK (1<<1)
1202 #define M98090_VS2ENN_SHIFT 1
1203 #define M98090_VS2ENN_WIDTH 1
1204 #define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
1205 #define M98090_VSENN_MASK (1<<0)
1207 #define M98090_VSENN_WIDTH 1
1208 #define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
1213 #define M98090_DMIC34BQEN_MASK (1<<4)
1215 #define M98090_DMIC34BQEN_WIDTH 1
1216 #define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
1217 #define M98090_ADCBQEN_MASK (1<<3)
1219 #define M98090_ADCBQEN_WIDTH 1
1220 #define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
1221 #define M98090_EQ3BANDEN_MASK (1<<2)
1223 #define M98090_EQ3BANDEN_WIDTH 1
1224 #define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
1225 #define M98090_EQ5BANDEN_MASK (1<<1)
1226 #define M98090_EQ5BANDEN_SHIFT 1
1227 #define M98090_EQ5BANDEN_WIDTH 1
1228 #define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
1229 #define M98090_EQ7BANDEN_MASK (1<<0)
1231 #define M98090_EQ7BANDEN_WIDTH 1
1232 #define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
1237 #define M98090_VCM_MODE_MASK (1<<0)
1239 #define M98090_VCM_MODE_WIDTH 1
1240 #define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
1245 #define M98090_PERFMODE_MASK (1<<1)
1246 #define M98090_PERFMODE_SHIFT 1
1247 #define M98090_PERFMODE_WIDTH 1
1248 #define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
1249 #define M98090_DACHP_MASK (1<<0)
1251 #define M98090_DACHP_WIDTH 1
1252 #define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
1257 #define M98090_OSR128_MASK (1<<2)
1259 #define M98090_OSR128_WIDTH 1
1260 #define M98090_ADCDITHER_MASK (1<<1)
1261 #define M98090_ADCDITHER_SHIFT 1
1262 #define M98090_ADCDITHER_WIDTH 1
1263 #define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
1264 #define M98090_ADCHP_MASK (1<<0)
1266 #define M98090_ADCHP_WIDTH 1
1267 #define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
1272 #define M98090_SHDNN_MASK (1<<7)
1274 #define M98090_SHDNN_WIDTH 1
1279 #define M98090_B0_1_HI_MASK (255<<0)
1282 #define M98090_B0_1_MID_MASK (255<<0)
1285 #define M98090_B0_1_LO_MASK (255<<0)
1288 #define M98090_B1_1_HI_MASK (255<<0)
1291 #define M98090_B1_1_MID_MASK (255<<0)
1294 #define M98090_B1_1_LO_MASK (255<<0)
1297 #define M98090_B2_1_HI_MASK (255<<0)
1300 #define M98090_B2_1_MID_MASK (255<<0)
1303 #define M98090_B2_1_LO_MASK (255<<0)
1306 #define M98090_A1_1_HI_MASK (255<<0)
1309 #define M98090_A1_1_MID_MASK (255<<0)
1312 #define M98090_A1_1_LO_MASK (255<<0)
1315 #define M98090_A2_1_HI_MASK (255<<0)
1318 #define M98090_A2_1_MID_MASK (255<<0)
1321 #define M98090_A2_1_LO_MASK (255<<0)
1332 #define M98090_REC_B0_HI_MASK (255<<0)
1335 #define M98090_REC_B0_MID_MASK (255<<0)
1338 #define M98090_REC_B0_LO_MASK (255<<0)
1341 #define M98090_REC_B1_HI_MASK (255<<0)
1344 #define M98090_REC_B1_MID_MASK (255<<0)
1347 #define M98090_REC_B1_LO_MASK (255<<0)
1350 #define M98090_REC_B2_HI_MASK (255<<0)
1353 #define M98090_REC_B2_MID_MASK (255<<0)
1356 #define M98090_REC_B2_LO_MASK (255<<0)
1359 #define M98090_REC_A1_HI_MASK (255<<0)
1362 #define M98090_REC_A1_MID_MASK (255<<0)
1365 #define M98090_REC_A1_LO_MASK (255<<0)
1368 #define M98090_REC_A2_HI_MASK (255<<0)
1371 #define M98090_REC_A2_MID_MASK (255<<0)
1374 #define M98090_REC_A2_LO_MASK (255<<0)
1384 #define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
1388 #define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
1396 #define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
1400 #define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
1408 #define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
1416 #define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
1420 #define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
1424 #define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
1428 #define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
1433 #define M98090_DMIC34_ZEROPAD_MASK (1<<4)
1435 #define M98090_DMIC34_ZEROPAD_WIDTH 1
1436 #define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
1444 #define M98090_DMIC34_B0_HI_MASK (255<<0)
1447 #define M98090_DMIC34_B0_MID_MASK (255<<0)
1450 #define M98090_DMIC34_B0_LO_MASK (255<<0)
1453 #define M98090_DMIC34_B1_HI_MASK (255<<0)
1456 #define M98090_DMIC34_B1_MID_MASK (255<<0)
1459 #define M98090_DMIC34_B1_LO_MASK (255<<0)
1462 #define M98090_DMIC34_B2_HI_MASK (255<<0)
1465 #define M98090_DMIC34_B2_MID_MASK (255<<0)
1468 #define M98090_DMIC34_B2_LO_MASK (255<<0)
1471 #define M98090_DMIC34_A1_HI_MASK (255<<0)
1474 #define M98090_DMIC34_A1_MID_MASK (255<<0)
1477 #define M98090_DMIC34_A1_LO_MASK (255<<0)
1480 #define M98090_DMIC34_A2_HI_MASK (255<<0)
1483 #define M98090_DMIC34_A2_MID_MASK (255<<0)
1486 #define M98090_DMIC34_A2_LO_MASK (255<<0)
1491 #define M98090_JACK_STATE_NO_HEADSET_2 1
1498 #define M98090_REVID_MASK (255<<0)
1501 #define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
1528 struct max98090_cdata dai[1];