21 /* VA macro registers */
267 	/* VA macro */
291 	/* VA core */
453 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable)  in va_clk_rsc_fs_gen_request()  argument
455 	struct regmap *regmap = va->regmap;  in va_clk_rsc_fs_gen_request()
486 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable)  in va_macro_mclk_enable()  argument
488 	struct regmap *regmap = va->regmap;  in va_macro_mclk_enable()
491 		va_clk_rsc_fs_gen_request(va, true);  in va_macro_mclk_enable()
495 		va_clk_rsc_fs_gen_request(va, false);  in va_macro_mclk_enable()
505 	struct va_macro *va = snd_soc_component_get_drvdata(comp);  in va_macro_mclk_event()  local
509 		return clk_prepare_enable(va->fsgen);  in va_macro_mclk_event()
511 		clk_disable_unprepare(va->fsgen);  in va_macro_mclk_event()
568 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_tx_mixer_get()  local
570 	if (test_bit(dec_id, &va->active_ch_mask[dai_id]))  in va_macro_tx_mixer_get()
591 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_tx_mixer_put()  local
594 		set_bit(dec_id, &va->active_ch_mask[dai_id]);  in va_macro_tx_mixer_put()
595 		va->active_ch_cnt[dai_id]++;  in va_macro_tx_mixer_put()
597 		clear_bit(dec_id, &va->active_ch_mask[dai_id]);  in va_macro_tx_mixer_put()
598 		va->active_ch_cnt[dai_id]--;  in va_macro_tx_mixer_put()
609 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_dmic_clk_enable()  local
619 		dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);  in va_dmic_clk_enable()
620 		dmic_clk_div = &(va->dmic_0_1_clk_div);  in va_dmic_clk_enable()
626 		dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);  in va_dmic_clk_enable()
627 		dmic_clk_div = &(va->dmic_2_3_clk_div);  in va_dmic_clk_enable()
633 		dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);  in va_dmic_clk_enable()
634 		dmic_clk_div = &(va->dmic_4_5_clk_div);  in va_dmic_clk_enable()
640 		dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);  in va_dmic_clk_enable()
641 		dmic_clk_div = &(va->dmic_6_7_clk_div);  in va_dmic_clk_enable()
652 		clk_div = va->dmic_clk_div;  in va_dmic_clk_enable()
693 			clk_div = va->dmic_clk_div;  in va_dmic_clk_enable()
695 				clk_div = va->dmic_clk_div;  in va_dmic_clk_enable()
744 	struct va_macro *va = snd_soc_component_get_drvdata(comp);  in va_macro_enable_dec()  local
761 			va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);  in va_macro_enable_dec()
824 	struct va_macro *va = snd_soc_component_get_drvdata(comp);  in va_macro_dec_mode_get()  local
828 	ucontrol->value.enumerated.item[0] = va->dec_mode[path];  in va_macro_dec_mode_get()
840 	struct va_macro *va = snd_soc_component_get_drvdata(comp);  in va_macro_dec_mode_put()  local
842 	va->dec_mode[path] = value;  in va_macro_dec_mode_put()
856 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_hw_params()  local
887 	for_each_set_bit(decimator, &va->active_ch_mask[dai->id],  in va_macro_hw_params()
903 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_get_channel_map()  local
909 		*tx_slot = va->active_ch_mask[dai->id];  in va_macro_get_channel_map()
910 		*tx_num = va->active_ch_cnt[dai->id];  in va_macro_get_channel_map()
922 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_digital_mute()  local
925 	for_each_set_bit(decimator, &va->active_ch_mask[dai->id],  in va_macro_digital_mute()
1127 	SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux),
1128 	SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux),
1129 	SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux),
1130 	SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux),
1142 	SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0,
1146 	SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0,
1150 	SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0,
1154 	SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0,
1158 	SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0,
1162 	SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0,
1166 	SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0,
1170 	SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0,
1174 	SND_SOC_DAPM_INPUT("VA SWR_ADC0"),
1175 	SND_SOC_DAPM_INPUT("VA SWR_ADC1"),
1176 	SND_SOC_DAPM_INPUT("VA SWR_ADC2"),
1177 	SND_SOC_DAPM_INPUT("VA SWR_ADC3"),
1178 	SND_SOC_DAPM_INPUT("VA SWR_MIC0"),
1179 	SND_SOC_DAPM_INPUT("VA SWR_MIC1"),
1180 	SND_SOC_DAPM_INPUT("VA SWR_MIC2"),
1181 	SND_SOC_DAPM_INPUT("VA SWR_MIC3"),
1182 	SND_SOC_DAPM_INPUT("VA SWR_MIC4"),
1183 	SND_SOC_DAPM_INPUT("VA SWR_MIC5"),
1184 	SND_SOC_DAPM_INPUT("VA SWR_MIC6"),
1185 	SND_SOC_DAPM_INPUT("VA SWR_MIC7"),
1187 	SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1192 	SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1197 	SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1202 	SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1221 	{"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1222 	{"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1223 	{"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1224 	{"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1226 	{"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1227 	{"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1228 	{"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1229 	{"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1231 	{"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1232 	{"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1233 	{"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1234 	{"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1236 	{"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1237 	{"VA DMIC MUX0", "DMIC0", "VA DMIC0"},
1238 	{"VA DMIC MUX0", "DMIC1", "VA DMIC1"},
1239 	{"VA DMIC MUX0", "DMIC2", "VA DMIC2"},
1240 	{"VA DMIC MUX0", "DMIC3", "VA DMIC3"},
1241 	{"VA DMIC MUX0", "DMIC4", "VA DMIC4"},
1242 	{"VA DMIC MUX0", "DMIC5", "VA DMIC5"},
1243 	{"VA DMIC MUX0", "DMIC6", "VA DMIC6"},
1244 	{"VA DMIC MUX0", "DMIC7", "VA DMIC7"},
1246 	{"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1247 	{"VA DMIC MUX1", "DMIC0", "VA DMIC0"},
1248 	{"VA DMIC MUX1", "DMIC1", "VA DMIC1"},
1249 	{"VA DMIC MUX1", "DMIC2", "VA DMIC2"},
1250 	{"VA DMIC MUX1", "DMIC3", "VA DMIC3"},
1251 	{"VA DMIC MUX1", "DMIC4", "VA DMIC4"},
1252 	{"VA DMIC MUX1", "DMIC5", "VA DMIC5"},
1253 	{"VA DMIC MUX1", "DMIC6", "VA DMIC6"},
1254 	{"VA DMIC MUX1", "DMIC7", "VA DMIC7"},
1256 	{"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1257 	{"VA DMIC MUX2", "DMIC0", "VA DMIC0"},
1258 	{"VA DMIC MUX2", "DMIC1", "VA DMIC1"},
1259 	{"VA DMIC MUX2", "DMIC2", "VA DMIC2"},
1260 	{"VA DMIC MUX2", "DMIC3", "VA DMIC3"},
1261 	{"VA DMIC MUX2", "DMIC4", "VA DMIC4"},
1262 	{"VA DMIC MUX2", "DMIC5", "VA DMIC5"},
1263 	{"VA DMIC MUX2", "DMIC6", "VA DMIC6"},
1264 	{"VA DMIC MUX2", "DMIC7", "VA DMIC7"},
1266 	{"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1267 	{"VA DMIC MUX3", "DMIC0", "VA DMIC0"},
1268 	{"VA DMIC MUX3", "DMIC1", "VA DMIC1"},
1269 	{"VA DMIC MUX3", "DMIC2", "VA DMIC2"},
1270 	{"VA DMIC MUX3", "DMIC3", "VA DMIC3"},
1271 	{"VA DMIC MUX3", "DMIC4", "VA DMIC4"},
1272 	{"VA DMIC MUX3", "DMIC5", "VA DMIC5"},
1273 	{"VA DMIC MUX3", "DMIC6", "VA DMIC6"},
1274 	{"VA DMIC MUX3", "DMIC7", "VA DMIC7"},
1276 	{ "VA DMIC0", NULL, "DMIC0 Pin" },
1277 	{ "VA DMIC1", NULL, "DMIC1 Pin" },
1278 	{ "VA DMIC2", NULL, "DMIC2 Pin" },
1279 	{ "VA DMIC3", NULL, "DMIC3 Pin" },
1280 	{ "VA DMIC4", NULL, "DMIC4 Pin" },
1281 	{ "VA DMIC5", NULL, "DMIC5 Pin" },
1282 	{ "VA DMIC6", NULL, "DMIC6 Pin" },
1283 	{ "VA DMIC7", NULL, "DMIC7 Pin" },
1323 	struct va_macro *va = snd_soc_component_get_drvdata(component);  in va_macro_component_probe()  local
1325 	snd_soc_component_init_regmap(component, va->regmap);  in va_macro_component_probe()
1331 	.name = "VA MACRO",
1343 	struct va_macro *va = to_va_macro(hw);  in fsgen_gate_enable()  local
1344 	struct regmap *regmap = va->regmap;  in fsgen_gate_enable()
1347 	if (va->has_swr_master) {  in fsgen_gate_enable()
1348 		ret = clk_prepare_enable(va->mclk);  in fsgen_gate_enable()
1353 	ret = va_macro_mclk_enable(va, true);  in fsgen_gate_enable()
1354 	if (va->has_swr_master)  in fsgen_gate_enable()
1363 	struct va_macro *va = to_va_macro(hw);  in fsgen_gate_disable()  local
1364 	struct regmap *regmap = va->regmap;  in fsgen_gate_disable()
1366 	if (va->has_swr_master)  in fsgen_gate_disable()
1370 	va_macro_mclk_enable(va, false);  in fsgen_gate_disable()
1371 	if (va->has_swr_master)  in fsgen_gate_disable()
1372 		clk_disable_unprepare(va->mclk);  in fsgen_gate_disable()
1377 	struct va_macro *va = to_va_macro(hw);  in fsgen_gate_is_enabled()  local
1380 	regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);  in fsgen_gate_is_enabled()
1391 static int va_macro_register_fsgen_output(struct va_macro *va)  in va_macro_register_fsgen_output()  argument
1393 	struct clk *parent = va->mclk;  in va_macro_register_fsgen_output()
1394 	struct device *dev = va->dev;  in va_macro_register_fsgen_output()
1401 	if (va->has_npl_clk)  in va_macro_register_fsgen_output()
1402 		parent = va->npl;  in va_macro_register_fsgen_output()
1413 	va->hw.init = &init;  in va_macro_register_fsgen_output()
1414 	ret = devm_clk_hw_register(va->dev, &va->hw);  in va_macro_register_fsgen_output()
1418 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);  in va_macro_register_fsgen_output()
1422 					      struct va_macro *va)  in va_macro_validate_dmic_sample_rate()  argument
1434 		va->dmic_clk_div = VA_MACRO_CLK_DIV_2;  in va_macro_validate_dmic_sample_rate()
1437 		va->dmic_clk_div = VA_MACRO_CLK_DIV_3;  in va_macro_validate_dmic_sample_rate()
1440 		va->dmic_clk_div = VA_MACRO_CLK_DIV_4;  in va_macro_validate_dmic_sample_rate()
1443 		va->dmic_clk_div = VA_MACRO_CLK_DIV_6;  in va_macro_validate_dmic_sample_rate()
1446 		va->dmic_clk_div = VA_MACRO_CLK_DIV_8;  in va_macro_validate_dmic_sample_rate()
1449 		va->dmic_clk_div = VA_MACRO_CLK_DIV_16;  in va_macro_validate_dmic_sample_rate()
1459 	dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",  in va_macro_validate_dmic_sample_rate()
1466 static void va_macro_set_lpass_codec_version(struct va_macro *va)  in va_macro_set_lpass_codec_version()  argument
1471 	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &core_id_0);  in va_macro_set_lpass_codec_version()
1472 	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &core_id_1);  in va_macro_set_lpass_codec_version()
1473 	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &core_id_2);  in va_macro_set_lpass_codec_version()
1491 		dev_warn(va->dev, "Unknown Codec version, ID: %02x / %02x / %02x\n",  in va_macro_set_lpass_codec_version()
1496 	dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));  in va_macro_set_lpass_codec_version()
1503 	struct va_macro *va;  in va_macro_probe()  local
1508 	va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL);  in va_macro_probe()
1509 	if (!va)  in va_macro_probe()
1512 	va->dev = dev;  in va_macro_probe()
1514 	va->macro = devm_clk_get_optional(dev, "macro");  in va_macro_probe()
1515 	if (IS_ERR(va->macro))  in va_macro_probe()
1516 		return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");  in va_macro_probe()
1518 	va->dcodec = devm_clk_get_optional(dev, "dcodec");  in va_macro_probe()
1519 	if (IS_ERR(va->dcodec))  in va_macro_probe()
1520 		return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");  in va_macro_probe()
1522 	va->mclk = devm_clk_get(dev, "mclk");  in va_macro_probe()
1523 	if (IS_ERR(va->mclk))  in va_macro_probe()
1524 		return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");  in va_macro_probe()
1526 	va->pds = lpass_macro_pds_init(dev);  in va_macro_probe()
1527 	if (IS_ERR(va->pds))  in va_macro_probe()
1528 		return PTR_ERR(va->pds);  in va_macro_probe()
1534 		va->dmic_clk_div = VA_MACRO_CLK_DIV_2;  in va_macro_probe()
1536 		ret = va_macro_validate_dmic_sample_rate(sample_rate, va);  in va_macro_probe()
1549 	va->regmap = devm_regmap_init_mmio(dev, base,  &va_regmap_config);  in va_macro_probe()
1550 	if (IS_ERR(va->regmap)) {  in va_macro_probe()
1555 	dev_set_drvdata(dev, va);  in va_macro_probe()
1558 	va->has_swr_master = data->has_swr_master;  in va_macro_probe()
1559 	va->has_npl_clk = data->has_npl_clk;  in va_macro_probe()
1562 	clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);  in va_macro_probe()
1564 	if (va->has_npl_clk) {  in va_macro_probe()
1565 		va->npl = devm_clk_get(dev, "npl");  in va_macro_probe()
1566 		if (IS_ERR(va->npl)) {  in va_macro_probe()
1567 			ret = PTR_ERR(va->npl);  in va_macro_probe()
1571 		clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ);  in va_macro_probe()
1574 	ret = clk_prepare_enable(va->macro);  in va_macro_probe()
1578 	ret = clk_prepare_enable(va->dcodec);  in va_macro_probe()
1582 	ret = clk_prepare_enable(va->mclk);  in va_macro_probe()
1586 	if (va->has_npl_clk) {  in va_macro_probe()
1587 		ret = clk_prepare_enable(va->npl);  in va_macro_probe()
1599 		va_macro_set_lpass_codec_version(va);  in va_macro_probe()
1601 	if (va->has_swr_master) {  in va_macro_probe()
1603 		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,  in va_macro_probe()
1606 		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,  in va_macro_probe()
1609 		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,  in va_macro_probe()
1615 	if (va->has_swr_master) {  in va_macro_probe()
1616 		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,  in va_macro_probe()
1618 		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,  in va_macro_probe()
1620 		regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,  in va_macro_probe()
1636 	ret = va_macro_register_fsgen_output(va);  in va_macro_probe()
1640 	va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");  in va_macro_probe()
1641 	if (IS_ERR(va->fsgen)) {  in va_macro_probe()
1642 		ret = PTR_ERR(va->fsgen);  in va_macro_probe()
1649 	if (va->has_npl_clk)  in va_macro_probe()
1650 		clk_disable_unprepare(va->npl);  in va_macro_probe()
1652 	clk_disable_unprepare(va->mclk);  in va_macro_probe()
1654 	clk_disable_unprepare(va->dcodec);  in va_macro_probe()
1656 	clk_disable_unprepare(va->macro);  in va_macro_probe()
1658 	lpass_macro_pds_exit(va->pds);  in va_macro_probe()
1665 	struct va_macro *va = dev_get_drvdata(&pdev->dev);  in va_macro_remove()  local
1667 	if (va->has_npl_clk)  in va_macro_remove()
1668 		clk_disable_unprepare(va->npl);  in va_macro_remove()
1670 	clk_disable_unprepare(va->mclk);  in va_macro_remove()
1671 	clk_disable_unprepare(va->dcodec);  in va_macro_remove()
1672 	clk_disable_unprepare(va->macro);  in va_macro_remove()
1674 	lpass_macro_pds_exit(va->pds);  in va_macro_remove()
1679 	struct va_macro *va = dev_get_drvdata(dev);  in va_macro_runtime_suspend()  local
1681 	regcache_cache_only(va->regmap, true);  in va_macro_runtime_suspend()
1682 	regcache_mark_dirty(va->regmap);  in va_macro_runtime_suspend()
1684 	if (va->has_npl_clk)  in va_macro_runtime_suspend()
1685 		clk_disable_unprepare(va->npl);  in va_macro_runtime_suspend()
1687 	clk_disable_unprepare(va->mclk);  in va_macro_runtime_suspend()
1694 	struct va_macro *va = dev_get_drvdata(dev);  in va_macro_runtime_resume()  local
1697 	ret = clk_prepare_enable(va->mclk);  in va_macro_runtime_resume()
1699 		dev_err(va->dev, "unable to prepare mclk\n");  in va_macro_runtime_resume()
1703 	if (va->has_npl_clk) {  in va_macro_runtime_resume()
1704 		ret = clk_prepare_enable(va->npl);  in va_macro_runtime_resume()
1706 			clk_disable_unprepare(va->mclk);  in va_macro_runtime_resume()
1707 			dev_err(va->dev, "unable to prepare npl\n");  in va_macro_runtime_resume()
1712 	regcache_cache_only(va->regmap, false);  in va_macro_runtime_resume()
1713 	regcache_sync(va->regmap);  in va_macro_runtime_resume()
1724 	{ .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1725 	{ .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1726 	{ .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1727 	{ .compatible = "qcom,sm8550-lpass-va-macro", .data = &sm8550_va_data },
1728 	{ .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
1745 MODULE_DESCRIPTION("VA macro driver");