Lines Matching full:dmic
41 /* Default divider for AMIC and DMIC clock: DIV2 */
760 unsigned int dmic; in tx_macro_update_smic_sel_v9() local
769 dmic = TX_ADC_TO_DMIC(val); in tx_macro_update_smic_sel_v9()
770 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); in tx_macro_update_smic_sel_v9()
782 unsigned int dmic; in tx_macro_update_smic_sel_v9_2() local
786 /* MSM DMIC */ in tx_macro_update_smic_sel_v9_2()
790 dmic = TX_ADC_TO_DMIC(val); in tx_macro_update_smic_sel_v9_2()
791 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); in tx_macro_update_smic_sel_v9_2()
846 if (widget->shift) /* MSM DMIC */ in tx_macro_put_dec_enum()
919 u16 adc_mux_reg, adc_reg, adc_n, dmic; in tx_macro_enable_dec() local
937 dmic = TX_ADC_TO_DMIC(adc_n); in tx_macro_enable_dec()
938 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic); in tx_macro_enable_dec()
1440 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1441 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1442 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1443 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1444 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1445 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1446 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1447 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1560 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1561 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1562 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1563 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1564 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1565 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1566 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1567 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1568 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1570 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1571 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1572 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1573 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1574 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1575 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1576 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1577 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1578 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1580 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1581 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1582 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1583 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1584 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1585 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1586 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1587 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1588 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1590 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1591 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1592 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1593 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1594 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1595 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1596 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1597 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1598 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1600 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1601 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1602 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1603 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1604 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1605 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1606 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1607 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1608 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1610 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1611 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1612 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1613 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1614 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1615 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1616 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1617 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1618 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1620 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1621 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1622 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1623 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1624 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1625 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1626 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1627 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1628 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1630 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1631 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1632 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1633 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1634 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1635 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1636 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1637 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1638 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},