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1 // SPDX-License-Identifier: GPL-2.0-only
3 * es8328.c -- ES8328 ALSA SoC Audio driver
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
99 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
100 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
101 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
123 if (es8328->deemph) { in es8328_set_deemph()
126 if (abs(deemph_settings[i].rate - es8328->playback_fs) < in es8328_set_deemph()
127 abs(deemph_settings[best].rate - es8328->playback_fs)) in es8328_set_deemph()
136 dev_dbg(component->dev, "Set deemphasis %d\n", val); in es8328_set_deemph()
148 ucontrol->value.integer.value[0] = es8328->deemph; in es8328_get_deemph()
157 unsigned int deemph = ucontrol->value.integer.value[0]; in es8328_put_deemph()
161 return -EINVAL; in es8328_put_deemph()
163 if (es8328->deemph == deemph) in es8328_put_deemph()
170 es8328->deemph = deemph; in es8328_put_deemph()
188 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
190 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
192 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
194 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
234 /* Left Mixer */
237 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
238 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
239 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
242 /* Right Mixer */
244 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
245 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
247 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
253 /* Left PGA Mux */
261 /* Right PGA Mux */
277 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
278 "Mono (Right)", "Digital Mono"};
287 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
289 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
292 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
295 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
299 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
301 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
304 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
306 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
334 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
336 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
339 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
342 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
346 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
348 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
350 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
352 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
368 { "Left Line Mux", "Line 1", "LINPUT1" },
369 { "Left Line Mux", "Line 2", "LINPUT2" },
370 { "Left Line Mux", "PGA", "Left PGA Mux" },
371 { "Left Line Mux", "Differential", "Differential Mux" },
373 { "Right Line Mux", "Line 1", "RINPUT1" },
374 { "Right Line Mux", "Line 2", "RINPUT2" },
375 { "Right Line Mux", "PGA", "Right PGA Mux" },
376 { "Right Line Mux", "Differential", "Differential Mux" },
378 { "Left PGA Mux", "Line 1", "LINPUT1" },
379 { "Left PGA Mux", "Line 2", "LINPUT2" },
380 { "Left PGA Mux", "Differential", "Differential Mux" },
382 { "Right PGA Mux", "Line 1", "RINPUT1" },
383 { "Right PGA Mux", "Line 2", "RINPUT2" },
384 { "Right PGA Mux", "Differential", "Differential Mux" },
391 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
392 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
393 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
395 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
396 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
397 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
399 { "Left ADC", NULL, "Left ADC Mux" },
400 { "Right ADC", NULL, "Right ADC Mux" },
406 { "Left ADC", NULL, "ADC DIG" },
407 { "Right ADC", NULL, "ADC DIG" },
411 { "Left Line Mux", "Line 1", "LINPUT1" },
412 { "Left Line Mux", "Line 2", "LINPUT2" },
413 { "Left Line Mux", "PGA", "Left PGA Mux" },
414 { "Left Line Mux", "Differential", "Differential Mux" },
416 { "Right Line Mux", "Line 1", "RINPUT1" },
417 { "Right Line Mux", "Line 2", "RINPUT2" },
418 { "Right Line Mux", "PGA", "Right PGA Mux" },
419 { "Right Line Mux", "Differential", "Differential Mux" },
421 { "Left Out 1", NULL, "Left DAC" },
422 { "Right Out 1", NULL, "Right DAC" },
423 { "Left Out 2", NULL, "Left DAC" },
424 { "Right Out 2", NULL, "Right DAC" },
426 { "Left Mixer", "Playback Switch", "Left DAC" },
427 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
428 { "Left Mixer", "Right Playback Switch", "Right DAC" },
429 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
431 { "Right Mixer", "Left Playback Switch", "Left DAC" },
432 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
433 { "Right Mixer", "Playback Switch", "Right DAC" },
434 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
440 { "Left DAC", NULL, "DAC DIG" },
441 { "Right DAC", NULL, "DAC DIG" },
443 { "Left Out 1", NULL, "Left Mixer" },
444 { "LOUT1", NULL, "Left Out 1" },
445 { "Right Out 1", NULL, "Right Mixer" },
446 { "ROUT1", NULL, "Right Out 1" },
448 { "Left Out 2", NULL, "Left Mixer" },
449 { "LOUT2", NULL, "Left Out 2" },
450 { "Right Out 2", NULL, "Right Mixer" },
451 { "ROUT2", NULL, "Right Out 2" },
456 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, in es8328_mute()
464 struct snd_soc_component *component = dai->component; in es8328_startup()
467 if (es8328->provider && es8328->sysclk_constraints) in es8328_startup()
468 snd_pcm_hw_constraint_list(substream->runtime, 0, in es8328_startup()
470 es8328->sysclk_constraints); in es8328_startup()
479 struct snd_soc_component *component = dai->component; in es8328_hw_params()
486 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in es8328_hw_params()
491 if (es8328->provider) { in es8328_hw_params()
492 if (!es8328->sysclk_constraints) { in es8328_hw_params()
493 dev_err(component->dev, "No MCLK configured\n"); in es8328_hw_params()
494 return -EINVAL; in es8328_hw_params()
497 for (i = 0; i < es8328->sysclk_constraints->count; i++) in es8328_hw_params()
498 if (es8328->sysclk_constraints->list[i] == in es8328_hw_params()
502 if (i == es8328->sysclk_constraints->count) { in es8328_hw_params()
503 dev_err(component->dev, in es8328_hw_params()
506 return -EINVAL; in es8328_hw_params()
508 ratio = es8328->mclk_ratios[i]; in es8328_hw_params()
511 es8328->mclkdiv2 = 0; in es8328_hw_params()
516 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); in es8328_hw_params()
535 return -EINVAL; in es8328_hw_params()
538 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in es8328_hw_params()
543 es8328->playback_fs = params_rate(params); in es8328_hw_params()
556 struct snd_soc_component *component = codec_dai->component; in es8328_set_sysclk()
569 es8328->sysclk_constraints = NULL; in es8328_set_sysclk()
570 es8328->mclk_ratios = NULL; in es8328_set_sysclk()
576 es8328->sysclk_constraints = &constraints_11289; in es8328_set_sysclk()
577 es8328->mclk_ratios = ratios_11289; in es8328_set_sysclk()
583 es8328->sysclk_constraints = &constraints_12288; in es8328_set_sysclk()
584 es8328->mclk_ratios = ratios_12288; in es8328_set_sysclk()
587 return -EINVAL; in es8328_set_sysclk()
590 es8328->mclkdiv2 = mclkdiv2; in es8328_set_sysclk()
597 struct snd_soc_component *component = codec_dai->component; in es8328_set_dai_fmt()
608 es8328->provider = true; in es8328_set_dai_fmt()
614 es8328->provider = false; in es8328_set_dai_fmt()
617 return -EINVAL; in es8328_set_dai_fmt()
635 return -EINVAL; in es8328_set_dai_fmt()
640 return -EINVAL; in es8328_set_dai_fmt()
711 .name = "es8328-hifi-analog",
737 clk_disable_unprepare(es8328->clk); in es8328_suspend()
739 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_suspend()
740 es8328->supplies); in es8328_suspend()
742 dev_err(component->dev, "unable to disable regulators\n"); in es8328_suspend()
750 struct regmap *regmap = dev_get_regmap(component->dev, NULL); in es8328_resume()
756 ret = clk_prepare_enable(es8328->clk); in es8328_resume()
758 dev_err(component->dev, "unable to enable clock\n"); in es8328_resume()
762 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_resume()
763 es8328->supplies); in es8328_resume()
765 dev_err(component->dev, "unable to enable regulators\n"); in es8328_resume()
772 dev_err(component->dev, "unable to sync regcache\n"); in es8328_resume()
786 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
787 es8328->supplies); in es8328_component_probe()
789 dev_err(component->dev, "unable to enable regulators\n"); in es8328_component_probe()
794 es8328->clk = devm_clk_get(component->dev, NULL); in es8328_component_probe()
795 if (IS_ERR(es8328->clk)) { in es8328_component_probe()
796 dev_err(component->dev, "codec clock missing or invalid\n"); in es8328_component_probe()
797 ret = PTR_ERR(es8328->clk); in es8328_component_probe()
801 ret = clk_prepare_enable(es8328->clk); in es8328_component_probe()
803 dev_err(component->dev, "unable to prepare codec clk\n"); in es8328_component_probe()
810 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
811 es8328->supplies); in es8328_component_probe()
821 clk_disable_unprepare(es8328->clk); in es8328_remove()
823 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_remove()
824 es8328->supplies); in es8328_remove()
866 return -ENOMEM; in es8328_probe()
868 es8328->regmap = regmap; in es8328_probe()
870 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) in es8328_probe()
871 es8328->supplies[i].supply = supply_names[i]; in es8328_probe()
873 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), in es8328_probe()
874 es8328->supplies); in es8328_probe()