Lines Matching +full:dc +full:- +full:dc +full:- +full:freq +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs43130.c -- CS43130 ALSA Soc Audio driver
25 #include <sound/soc-dapm.h>
239 dev_dbg(cs43130->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n", in cs43130_pll_config()
240 cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
242 pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int); in cs43130_pll_config()
244 return -EINVAL; in cs43130_pll_config()
246 if (pll_entry->pll_cal_ratio == 0) { in cs43130_pll_config()
247 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, in cs43130_pll_config()
250 cs43130->pll_bypass = true; in cs43130_pll_config()
254 cs43130->pll_bypass = false; in cs43130_pll_config()
256 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2, in cs43130_pll_config()
258 pll_entry->pll_div_frac >> in cs43130_pll_config()
260 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3, in cs43130_pll_config()
262 pll_entry->pll_div_frac >> in cs43130_pll_config()
264 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4, in cs43130_pll_config()
266 pll_entry->pll_div_frac >> in cs43130_pll_config()
268 regmap_write(cs43130->regmap, CS43130_PLL_SET_5, in cs43130_pll_config()
269 pll_entry->pll_div_int); in cs43130_pll_config()
270 regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout); in cs43130_pll_config()
271 regmap_write(cs43130->regmap, CS43130_PLL_SET_7, in cs43130_pll_config()
272 pll_entry->pll_cal_ratio); in cs43130_pll_config()
273 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8, in cs43130_pll_config()
275 pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); in cs43130_pll_config()
276 regmap_write(cs43130->regmap, CS43130_PLL_SET_9, in cs43130_pll_config()
277 pll_entry->sclk_prediv); in cs43130_pll_config()
278 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1, in cs43130_pll_config()
301 cs43130->mclk = freq_in; in cs43130_set_pll()
304 dev_err(cs43130->dev, in cs43130_set_pll()
306 return -EINVAL; in cs43130_set_pll()
311 cs43130->mclk_int = freq_out; in cs43130_set_pll()
314 cs43130->mclk_int = freq_out; in cs43130_set_pll()
317 dev_err(cs43130->dev, in cs43130_set_pll()
319 return -EINVAL; in cs43130_set_pll()
323 dev_dbg(cs43130->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass); in cs43130_set_pll()
332 if (cs43130->has_irq_line) { in cs43130_wait_for_completion()
335 return -ETIMEDOUT; in cs43130_wait_for_completion()
340 if (to_poll == &cs43130->xtal_rdy) { in cs43130_wait_for_completion()
343 } else if (to_poll == &cs43130->pll_rdy) { in cs43130_wait_for_completion()
347 return -EINVAL; in cs43130_wait_for_completion()
350 return regmap_read_poll_timeout(cs43130->regmap, CS43130_INT_STATUS_1 + offset, in cs43130_wait_for_completion()
362 if (src == cs43130->mclk_int_src) { in cs43130_change_clksrc()
367 switch (cs43130->mclk_int) { in cs43130_change_clksrc()
375 dev_err(cs43130->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int); in cs43130_change_clksrc()
376 return -EINVAL; in cs43130_change_clksrc()
381 cs43130->pll_bypass = true; in cs43130_change_clksrc()
382 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT; in cs43130_change_clksrc()
383 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { in cs43130_change_clksrc()
384 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
388 reinit_completion(&cs43130->xtal_rdy); in cs43130_change_clksrc()
389 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
391 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
393 ret = cs43130_wait_for_completion(cs43130, &cs43130->xtal_rdy, 100); in cs43130_change_clksrc()
394 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
398 dev_err(cs43130->dev, "Error waiting for XTAL_READY interrupt: %d\n", ret); in cs43130_change_clksrc()
403 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
406 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
411 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
416 cs43130->pll_bypass = false; in cs43130_change_clksrc()
417 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL; in cs43130_change_clksrc()
418 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { in cs43130_change_clksrc()
419 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
423 reinit_completion(&cs43130->xtal_rdy); in cs43130_change_clksrc()
424 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
426 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
428 ret = cs43130_wait_for_completion(cs43130, &cs43130->xtal_rdy, 100); in cs43130_change_clksrc()
429 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
433 dev_err(cs43130->dev, "Error waiting for XTAL_READY interrupt: %d\n", ret); in cs43130_change_clksrc()
438 reinit_completion(&cs43130->pll_rdy); in cs43130_change_clksrc()
439 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
441 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
443 ret = cs43130_wait_for_completion(cs43130, &cs43130->pll_rdy, 100); in cs43130_change_clksrc()
444 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_change_clksrc()
448 dev_err(cs43130->dev, "Error waiting for PLL_READY interrupt: %d\n", ret); in cs43130_change_clksrc()
452 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
455 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
461 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; in cs43130_change_clksrc()
463 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
466 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1, in cs43130_change_clksrc()
471 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
474 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL, in cs43130_change_clksrc()
479 dev_err(cs43130->dev, "Invalid MCLK source value\n"); in cs43130_change_clksrc()
480 return -EINVAL; in cs43130_change_clksrc()
513 return -EINVAL; in cs43130_set_bitwidth()
519 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
521 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
523 CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit); in cs43130_set_bitwidth()
527 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
529 CS43130_CH_BITSIZE_MASK, bw_map->ch_bit); in cs43130_set_bitwidth()
531 CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit << in cs43130_set_bitwidth()
535 return -EINVAL; in cs43130_set_bitwidth()
596 switch (cs43130->dais[dai_id].dai_format) { in cs43130_set_sp_fmt()
618 return -EINVAL; in cs43130_set_sp_fmt()
621 switch (cs43130->dais[dai_id].dai_invert) { in cs43130_set_sp_fmt()
639 return -EINVAL; in cs43130_set_sp_fmt()
642 switch (cs43130->dais[dai_id].dai_mode) { in cs43130_set_sp_fmt()
650 return -EINVAL; in cs43130_set_sp_fmt()
655 loc_ch2 = bitwidth_sclk * (params_channels(params) - 1); in cs43130_set_sp_fmt()
673 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1, in cs43130_set_sp_fmt()
674 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
676 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2, in cs43130_set_sp_fmt()
677 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
679 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1, in cs43130_set_sp_fmt()
680 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
682 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2, in cs43130_set_sp_fmt()
683 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
685 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data); in cs43130_set_sp_fmt()
686 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1); in cs43130_set_sp_fmt()
687 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2); in cs43130_set_sp_fmt()
688 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN, in cs43130_set_sp_fmt()
690 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN, in cs43130_set_sp_fmt()
692 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data); in cs43130_set_sp_fmt()
695 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1, in cs43130_set_sp_fmt()
696 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
698 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2, in cs43130_set_sp_fmt()
699 CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >> in cs43130_set_sp_fmt()
701 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1, in cs43130_set_sp_fmt()
702 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
704 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2, in cs43130_set_sp_fmt()
705 CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >> in cs43130_set_sp_fmt()
707 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data); in cs43130_set_sp_fmt()
708 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1); in cs43130_set_sp_fmt()
709 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2); in cs43130_set_sp_fmt()
710 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN, in cs43130_set_sp_fmt()
712 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN, in cs43130_set_sp_fmt()
714 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data); in cs43130_set_sp_fmt()
717 return -EINVAL; in cs43130_set_sp_fmt()
722 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
728 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
734 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
740 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int, in cs43130_set_sp_fmt()
746 return -EINVAL; in cs43130_set_sp_fmt()
750 return -EINVAL; in cs43130_set_sp_fmt()
755 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1, in cs43130_set_sp_fmt()
756 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
758 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2, in cs43130_set_sp_fmt()
759 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
761 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1, in cs43130_set_sp_fmt()
762 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
764 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2, in cs43130_set_sp_fmt()
765 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
769 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1, in cs43130_set_sp_fmt()
770 (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
772 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2, in cs43130_set_sp_fmt()
773 (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
775 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1, in cs43130_set_sp_fmt()
776 (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> in cs43130_set_sp_fmt()
778 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2, in cs43130_set_sp_fmt()
779 (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> in cs43130_set_sp_fmt()
783 return -EINVAL; in cs43130_set_sp_fmt()
816 struct snd_soc_component *component = dai->component; in cs43130_dsd_hw_params()
821 mutex_lock(&cs43130->clk_mutex); in cs43130_dsd_hw_params()
822 if (!cs43130->clk_req) { in cs43130_dsd_hw_params()
829 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); in cs43130_dsd_hw_params()
830 if (cs43130->pll_bypass) in cs43130_dsd_hw_params()
836 cs43130->clk_req++; in cs43130_dsd_hw_params()
837 if (cs43130->clk_req == 2) in cs43130_dsd_hw_params()
838 cs43130_pcm_dsd_mix(true, cs43130->regmap); in cs43130_dsd_hw_params()
839 mutex_unlock(&cs43130->clk_mutex); in cs43130_dsd_hw_params()
849 dev_err(cs43130->dev, "Rate(%u) not supported\n", in cs43130_dsd_hw_params()
851 return -EINVAL; in cs43130_dsd_hw_params()
854 if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) in cs43130_dsd_hw_params()
855 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, in cs43130_dsd_hw_params()
858 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG, in cs43130_dsd_hw_params()
861 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_dsd_hw_params()
864 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_dsd_hw_params()
875 struct snd_soc_component *component = dai->component; in cs43130_hw_params()
878 unsigned int sclk = cs43130->dais[dai->id].sclk; in cs43130_hw_params()
884 mutex_lock(&cs43130->clk_mutex); in cs43130_hw_params()
885 if (!cs43130->clk_req) { in cs43130_hw_params()
892 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk); in cs43130_hw_params()
893 if (cs43130->pll_bypass) in cs43130_hw_params()
899 cs43130->clk_req++; in cs43130_hw_params()
900 if (cs43130->clk_req == 2) in cs43130_hw_params()
901 cs43130_pcm_dsd_mix(true, cs43130->regmap); in cs43130_hw_params()
902 mutex_unlock(&cs43130->clk_mutex); in cs43130_hw_params()
904 switch (dai->id) { in cs43130_hw_params()
907 /* DoP bitwidth is always 24-bit */ in cs43130_hw_params()
920 dev_err(cs43130->dev, "Rate(%u) not supported\n", in cs43130_hw_params()
922 return -EINVAL; in cs43130_hw_params()
925 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
932 return -EINVAL; in cs43130_hw_params()
934 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val); in cs43130_hw_params()
937 dev_err(cs43130->dev, "Invalid DAI (%d)\n", dai->id); in cs43130_hw_params()
938 return -EINVAL; in cs43130_hw_params()
941 switch (dai->id) { in cs43130_hw_params()
943 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
948 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2, in cs43130_hw_params()
954 if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) in cs43130_hw_params()
961 dev_err(cs43130->dev, "SCLK freq is not set\n"); in cs43130_hw_params()
962 return -EINVAL; in cs43130_hw_params()
967 dev_err(cs43130->dev, "Format not supported: SCLK freq is too low\n"); in cs43130_hw_params()
968 return -EINVAL; in cs43130_hw_params()
971 dev_dbg(cs43130->dev, in cs43130_hw_params()
975 dev_dbg(cs43130->dev, in cs43130_hw_params()
979 cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap); in cs43130_hw_params()
980 cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130); in cs43130_hw_params()
988 struct snd_soc_component *component = dai->component; in cs43130_hw_free()
991 mutex_lock(&cs43130->clk_mutex); in cs43130_hw_free()
992 cs43130->clk_req--; in cs43130_hw_free()
993 if (!cs43130->clk_req) { in cs43130_hw_free()
996 cs43130_pcm_dsd_mix(false, cs43130->regmap); in cs43130_hw_free()
998 mutex_unlock(&cs43130->clk_mutex); in cs43130_hw_free()
1003 static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
1006 "Left-Right Ch",
1007 "Left-Left Ch",
1008 "Right-Left Ch",
1009 "Right-Right Ch",
1063 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in cs43130_pcm_ch_put()
1064 unsigned int *item = ucontrol->value.enumerated.item; in cs43130_pcm_ch_put()
1069 if (item[0] >= e->items) in cs43130_pcm_ch_put()
1070 return -EINVAL; in cs43130_pcm_ch_put()
1071 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; in cs43130_pcm_ch_put()
1073 switch (cs43130->dev_id) { in cs43130_pcm_ch_put()
1077 regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq, in cs43130_pcm_ch_put()
1080 regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq, in cs43130_pcm_ch_put()
1126 SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0),
1127 SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0),
1186 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_dsd_event()
1191 switch (cs43130->dev_id) { in cs43130_dsd_event()
1194 regmap_multi_reg_write(cs43130->regmap, dsd_seq, in cs43130_dsd_event()
1200 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1, in cs43130_dsd_event()
1202 switch (cs43130->dev_id) { in cs43130_dsd_event()
1205 regmap_multi_reg_write(cs43130->regmap, unmute_seq, in cs43130_dsd_event()
1211 switch (cs43130->dev_id) { in cs43130_dsd_event()
1214 regmap_multi_reg_write(cs43130->regmap, mute_seq, in cs43130_dsd_event()
1216 regmap_update_bits(cs43130->regmap, in cs43130_dsd_event()
1227 regmap_update_bits(cs43130->regmap, in cs43130_dsd_event()
1234 dev_err(cs43130->dev, "Invalid event = 0x%x\n", event); in cs43130_dsd_event()
1235 return -EINVAL; in cs43130_dsd_event()
1243 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_pcm_event()
1248 switch (cs43130->dev_id) { in cs43130_pcm_event()
1251 regmap_multi_reg_write(cs43130->regmap, pcm_seq, in cs43130_pcm_event()
1257 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1, in cs43130_pcm_event()
1259 switch (cs43130->dev_id) { in cs43130_pcm_event()
1262 regmap_multi_reg_write(cs43130->regmap, unmute_seq, in cs43130_pcm_event()
1268 switch (cs43130->dev_id) { in cs43130_pcm_event()
1271 regmap_multi_reg_write(cs43130->regmap, mute_seq, in cs43130_pcm_event()
1273 regmap_update_bits(cs43130->regmap, in cs43130_pcm_event()
1284 regmap_update_bits(cs43130->regmap, in cs43130_pcm_event()
1291 dev_err(cs43130->dev, "Invalid event = 0x%x\n", event); in cs43130_pcm_event()
1292 return -EINVAL; in cs43130_pcm_event()
1312 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_dac_event()
1317 switch (cs43130->dev_id) { in cs43130_dac_event()
1320 regmap_multi_reg_write(cs43130->regmap, pop_free_seq, in cs43130_dac_event()
1325 regmap_multi_reg_write(cs43130->regmap, pop_free_seq2, in cs43130_dac_event()
1333 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99); in cs43130_dac_event()
1335 switch (cs43130->dev_id) { in cs43130_dac_event()
1338 regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq, in cs43130_dac_event()
1341 * Per datasheet, Sec. PCM Power-Up Sequence. in cs43130_dac_event()
1346 regmap_write(cs43130->regmap, CS43130_DXD12, 0); in cs43130_dac_event()
1351 regmap_write(cs43130->regmap, CS43130_DXD13, 0); in cs43130_dac_event()
1355 regmap_write(cs43130->regmap, CS43130_DXD1, 0); in cs43130_dac_event()
1358 switch (cs43130->dev_id) { in cs43130_dac_event()
1361 regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq, in cs43130_dac_event()
1367 dev_err(cs43130->dev, "Invalid DAC event = 0x%x\n", event); in cs43130_dac_event()
1368 return -EINVAL; in cs43130_dac_event()
1392 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs43130_hpin_event()
1397 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq, in cs43130_hpin_event()
1401 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq, in cs43130_hpin_event()
1405 dev_err(cs43130->dev, "Invalid HPIN event = 0x%x\n", event); in cs43130_hpin_event()
1406 return -EINVAL; in cs43130_hpin_event()
1491 return snd_pcm_hw_constraint_list(substream->runtime, 0, in cs43130_pcm_startup()
1508 return snd_pcm_hw_constraint_list(substream->runtime, 0, in cs43130_dop_startup()
1515 struct snd_soc_component *component = codec_dai->component; in cs43130_pcm_set_fmt()
1520 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; in cs43130_pcm_set_fmt()
1523 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; in cs43130_pcm_set_fmt()
1526 dev_err(cs43130->dev, "unsupported mode\n"); in cs43130_pcm_set_fmt()
1527 return -EINVAL; in cs43130_pcm_set_fmt()
1532 cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_NB_NF; in cs43130_pcm_set_fmt()
1535 cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_IB_NF; in cs43130_pcm_set_fmt()
1538 cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_NB_IF; in cs43130_pcm_set_fmt()
1541 cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_IB_IF; in cs43130_pcm_set_fmt()
1544 dev_err(cs43130->dev, "Unsupported invert mode 0x%x\n", in cs43130_pcm_set_fmt()
1546 return -EINVAL; in cs43130_pcm_set_fmt()
1551 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S; in cs43130_pcm_set_fmt()
1554 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J; in cs43130_pcm_set_fmt()
1557 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A; in cs43130_pcm_set_fmt()
1560 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B; in cs43130_pcm_set_fmt()
1563 dev_err(cs43130->dev, in cs43130_pcm_set_fmt()
1565 return -EINVAL; in cs43130_pcm_set_fmt()
1568 dev_dbg(cs43130->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n", in cs43130_pcm_set_fmt()
1569 codec_dai->id, in cs43130_pcm_set_fmt()
1570 cs43130->dais[codec_dai->id].dai_mode, in cs43130_pcm_set_fmt()
1571 cs43130->dais[codec_dai->id].dai_format); in cs43130_pcm_set_fmt()
1578 struct snd_soc_component *component = codec_dai->component; in cs43130_dsd_set_fmt()
1583 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; in cs43130_dsd_set_fmt()
1586 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; in cs43130_dsd_set_fmt()
1589 dev_err(cs43130->dev, "Unsupported DAI format.\n"); in cs43130_dsd_set_fmt()
1590 return -EINVAL; in cs43130_dsd_set_fmt()
1593 dev_dbg(cs43130->dev, "dai_mode = 0x%x\n", in cs43130_dsd_set_fmt()
1594 cs43130->dais[codec_dai->id].dai_mode); in cs43130_dsd_set_fmt()
1600 int clk_id, unsigned int freq, int dir) in cs43130_set_sysclk() argument
1602 struct snd_soc_component *component = codec_dai->component; in cs43130_set_sysclk()
1605 cs43130->dais[codec_dai->id].sclk = freq; in cs43130_set_sysclk()
1606 dev_dbg(cs43130->dev, "dai_id = %d, sclk = %u\n", codec_dai->id, in cs43130_set_sysclk()
1607 cs43130->dais[codec_dai->id].sclk); in cs43130_set_sysclk()
1637 .name = "cs43130-asp-pcm",
1650 .name = "cs43130-asp-dop",
1663 .name = "cs43130-xsp-dop",
1676 .name = "cs43130-xsp-dsd",
1691 int clk_id, int source, unsigned int freq, in cs43130_component_set_sysclk() argument
1696 dev_dbg(cs43130->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n", in cs43130_component_set_sysclk()
1697 clk_id, source, freq, dir); in cs43130_component_set_sysclk()
1699 switch (freq) { in cs43130_component_set_sysclk()
1702 cs43130->mclk = freq; in cs43130_component_set_sysclk()
1705 dev_err(cs43130->dev, "Invalid MCLK INT freq: %u\n", freq); in cs43130_component_set_sysclk()
1706 return -EINVAL; in cs43130_component_set_sysclk()
1710 cs43130->pll_bypass = true; in cs43130_component_set_sysclk()
1712 dev_err(cs43130->dev, "Invalid MCLK source\n"); in cs43130_component_set_sysclk()
1713 return -EINVAL; in cs43130_component_set_sysclk()
1721 /* AC freq is counted in 5.94Hz step. */ in cs43130_get_ac_reg_val()
1730 if (!cs43130->hpload_done) in cs43130_show_dc()
1733 return sysfs_emit(buf, "%u\n", cs43130->hpload_dc[ch]); in cs43130_show_dc()
1767 if (cs43130->hpload_done && cs43130->ac_meas) { in cs43130_show_ac()
1770 cs43130->hpload_ac[i][ch]); in cs43130_show_ac()
2008 regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, ®); in cs43130_update_hpload()
2017 regmap_read(cs43130->regmap, addr, ®); in cs43130_update_hpload()
2019 regmap_read(cs43130->regmap, addr + 1, ®); in cs43130_update_hpload()
2024 cs43130->hpload_dc[HP_LEFT] = impedance; in cs43130_update_hpload()
2026 cs43130->hpload_dc[HP_RIGHT] = impedance; in cs43130_update_hpload()
2028 dev_dbg(cs43130->dev, "HP DC impedance (Ch %u): %u\n", !left_ch, in cs43130_update_hpload()
2032 cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance; in cs43130_update_hpload()
2034 cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance; in cs43130_update_hpload()
2036 dev_dbg(cs43130->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n", in cs43130_update_hpload()
2037 cs43130->ac_freq[ac_idx], !left_ch, impedance); in cs43130_update_hpload()
2051 reinit_completion(&cs43130->hpload_evt); in cs43130_hpload_proc()
2054 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]); in cs43130_hpload_proc()
2055 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1, in cs43130_hpload_proc()
2057 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1, in cs43130_hpload_proc()
2060 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2, in cs43130_hpload_proc()
2065 regmap_multi_reg_write(cs43130->regmap, seq, in cs43130_hpload_proc()
2068 ret = wait_for_completion_timeout(&cs43130->hpload_evt, in cs43130_hpload_proc()
2070 regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk); in cs43130_hpload_proc()
2072 dev_err(cs43130->dev, "Timeout waiting for HPLOAD interrupt\n"); in cs43130_hpload_proc()
2073 return -ETIMEDOUT; in cs43130_hpload_proc()
2076 dev_dbg(cs43130->dev, "HP load stat: %x, INT_MASK_4: %x\n", in cs43130_hpload_proc()
2077 cs43130->hpload_stat, msk); in cs43130_hpload_proc()
2078 if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT | in cs43130_hpload_proc()
2081 !(cs43130->hpload_stat & rslt_msk)) { in cs43130_hpload_proc()
2082 dev_dbg(cs43130->dev, "HP load measure failed\n"); in cs43130_hpload_proc()
2083 return -1; in cs43130_hpload_proc()
2128 component = cs43130->component; in cs43130_imp_meas()
2130 if (!cs43130->mclk) in cs43130_imp_meas()
2133 cs43130->hpload_done = false; in cs43130_imp_meas()
2135 mutex_lock(&cs43130->clk_mutex); in cs43130_imp_meas()
2136 if (!cs43130->clk_req) { in cs43130_imp_meas()
2138 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M); in cs43130_imp_meas()
2139 if (cs43130->pll_bypass) in cs43130_imp_meas()
2145 cs43130->clk_req++; in cs43130_imp_meas()
2146 mutex_unlock(&cs43130->clk_mutex); in cs43130_imp_meas()
2148 regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, ®); in cs43130_imp_meas()
2150 switch (cs43130->dev_id) { in cs43130_imp_meas()
2160 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id); in cs43130_imp_meas()
2175 if (cs43130->ac_meas && in cs43130_imp_meas()
2177 ac_idx < CS43130_AC_FREQ - 1) { in cs43130_imp_meas()
2184 cs43130->hpload_done = true; in cs43130_imp_meas()
2186 if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD) in cs43130_imp_meas()
2187 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT, in cs43130_imp_meas()
2190 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE, in cs43130_imp_meas()
2193 dev_dbg(cs43130->dev, "Set HP output control. DC threshold\n"); in cs43130_imp_meas()
2195 dev_dbg(cs43130->dev, "DC threshold[%d]: %u.\n", i, in cs43130_imp_meas()
2196 cs43130->dc_threshold[i]); in cs43130_imp_meas()
2198 cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT], in cs43130_imp_meas()
2199 cs43130->dc_threshold); in cs43130_imp_meas()
2202 switch (cs43130->dev_id) { in cs43130_imp_meas()
2215 regmap_multi_reg_write(cs43130->regmap, hp_cln_seq, in cs43130_imp_meas()
2218 mutex_lock(&cs43130->clk_mutex); in cs43130_imp_meas()
2219 cs43130->clk_req--; in cs43130_imp_meas()
2221 if (!cs43130->clk_req) in cs43130_imp_meas()
2223 mutex_unlock(&cs43130->clk_mutex); in cs43130_imp_meas()
2235 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i, in cs43130_irq_thread()
2237 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i, in cs43130_irq_thread()
2251 complete(&cs43130->xtal_rdy); in cs43130_irq_thread()
2256 complete(&cs43130->pll_rdy); in cs43130_irq_thread()
2261 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2262 dev_err(cs43130->dev, in cs43130_irq_thread()
2263 "DC load has not completed before AC load (%x)\n", in cs43130_irq_thread()
2264 cs43130->hpload_stat); in cs43130_irq_thread()
2265 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2270 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2271 dev_err(cs43130->dev, "HP unplugged during measurement (%x)\n", in cs43130_irq_thread()
2272 cs43130->hpload_stat); in cs43130_irq_thread()
2273 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2278 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2279 dev_err(cs43130->dev, "HP load out of range (%x)\n", in cs43130_irq_thread()
2280 cs43130->hpload_stat); in cs43130_irq_thread()
2281 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2286 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2287 dev_dbg(cs43130->dev, "HP AC load measurement done (%x)\n", in cs43130_irq_thread()
2288 cs43130->hpload_stat); in cs43130_irq_thread()
2289 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2294 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2295 dev_dbg(cs43130->dev, "HP DC load measurement done (%x)\n", in cs43130_irq_thread()
2296 cs43130->hpload_stat); in cs43130_irq_thread()
2297 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2302 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2303 dev_dbg(cs43130->dev, "HP load state machine on done (%x)\n", in cs43130_irq_thread()
2304 cs43130->hpload_stat); in cs43130_irq_thread()
2305 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2310 cs43130->hpload_stat = stickies[3]; in cs43130_irq_thread()
2311 dev_dbg(cs43130->dev, "HP load state machine off done (%x)\n", in cs43130_irq_thread()
2312 cs43130->hpload_stat); in cs43130_irq_thread()
2313 complete(&cs43130->hpload_evt); in cs43130_irq_thread()
2318 dev_err(cs43130->dev, "Crystal err: clock is not running\n"); in cs43130_irq_thread()
2323 dev_dbg(cs43130->dev, "HP unplugged\n"); in cs43130_irq_thread()
2324 cs43130->hpload_done = false; in cs43130_irq_thread()
2325 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK); in cs43130_irq_thread()
2330 if (cs43130->dc_meas && !cs43130->hpload_done && in cs43130_irq_thread()
2331 !work_busy(&cs43130->work)) { in cs43130_irq_thread()
2332 dev_dbg(cs43130->dev, "HP load queue work\n"); in cs43130_irq_thread()
2333 queue_work(cs43130->wq, &cs43130->work); in cs43130_irq_thread()
2336 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL, in cs43130_irq_thread()
2348 struct snd_soc_card *card = component->card; in cs43130_probe()
2351 cs43130->component = component; in cs43130_probe()
2353 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) { in cs43130_probe()
2354 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET, in cs43130_probe()
2356 cs43130->xtal_ibias); in cs43130_probe()
2357 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_probe()
2362 &cs43130->jack); in cs43130_probe()
2364 dev_err(cs43130->dev, "Cannot create jack\n"); in cs43130_probe()
2368 cs43130->hpload_done = false; in cs43130_probe()
2369 if (cs43130->dc_meas) { in cs43130_probe()
2370 ret = sysfs_create_groups(&cs43130->dev->kobj, hpload_groups); in cs43130_probe()
2374 cs43130->wq = create_singlethread_workqueue("cs43130_hp"); in cs43130_probe()
2375 if (!cs43130->wq) { in cs43130_probe()
2376 sysfs_remove_groups(&cs43130->dev->kobj, hpload_groups); in cs43130_probe()
2377 return -ENOMEM; in cs43130_probe()
2379 INIT_WORK(&cs43130->work, cs43130_imp_meas); in cs43130_probe()
2382 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, ®); in cs43130_probe()
2383 regmap_read(cs43130->regmap, CS43130_HP_STATUS, ®); in cs43130_probe()
2384 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_probe()
2386 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, in cs43130_probe()
2388 regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT, in cs43130_probe()
2406 .num_dapm_widgets = ARRAY_SIZE(hp_widgets) - NUM_ANALOG_WIDGETS,
2408 .num_dapm_routes = ARRAY_SIZE(hp_routes) - NUM_ANALOG_ROUTES,
2453 if (device_property_read_u32(cs43130->dev, "cirrus,xtal-ibias", &val) < 0) { in cs43130_handle_device_data()
2455 cs43130->xtal_ibias = CS43130_XTAL_UNUSED; in cs43130_handle_device_data()
2461 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA; in cs43130_handle_device_data()
2464 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA; in cs43130_handle_device_data()
2467 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA; in cs43130_handle_device_data()
2470 dev_err(cs43130->dev, in cs43130_handle_device_data()
2471 "Invalid cirrus,xtal-ibias value: %d\n", val); in cs43130_handle_device_data()
2472 return -EINVAL; in cs43130_handle_device_data()
2475 cs43130->dc_meas = device_property_read_bool(cs43130->dev, "cirrus,dc-measure"); in cs43130_handle_device_data()
2476 cs43130->ac_meas = device_property_read_bool(cs43130->dev, "cirrus,ac-measure"); in cs43130_handle_device_data()
2478 if (!device_property_read_u16_array(cs43130->dev, "cirrus,ac-freq", cs43130->ac_freq, in cs43130_handle_device_data()
2481 cs43130->ac_freq[i] = cs43130_ac_freq[i]; in cs43130_handle_device_data()
2484 if (!device_property_read_u16_array(cs43130->dev, "cirrus,dc-threshold", in cs43130_handle_device_data()
2485 cs43130->dc_threshold, in cs43130_handle_device_data()
2488 cs43130->dc_threshold[i] = cs43130_dc_threshold[i]; in cs43130_handle_device_data()
2502 cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL); in cs43130_i2c_probe()
2504 return -ENOMEM; in cs43130_i2c_probe()
2506 cs43130->dev = &client->dev; in cs43130_i2c_probe()
2510 cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap); in cs43130_i2c_probe()
2511 if (IS_ERR(cs43130->regmap)) { in cs43130_i2c_probe()
2512 ret = PTR_ERR(cs43130->regmap); in cs43130_i2c_probe()
2516 if (dev_fwnode(cs43130->dev)) { in cs43130_i2c_probe()
2522 for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++) in cs43130_i2c_probe()
2523 cs43130->supplies[i].supply = cs43130_supply_names[i]; in cs43130_i2c_probe()
2525 ret = devm_regulator_bulk_get(cs43130->dev, in cs43130_i2c_probe()
2526 ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2527 cs43130->supplies); in cs43130_i2c_probe()
2529 dev_err(cs43130->dev, "Failed to request supplies: %d\n", ret); in cs43130_i2c_probe()
2532 ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2533 cs43130->supplies); in cs43130_i2c_probe()
2535 dev_err(cs43130->dev, "Failed to enable supplies: %d\n", ret); in cs43130_i2c_probe()
2539 cs43130->reset_gpio = devm_gpiod_get_optional(cs43130->dev, in cs43130_i2c_probe()
2541 if (IS_ERR(cs43130->reset_gpio)) { in cs43130_i2c_probe()
2542 ret = PTR_ERR(cs43130->reset_gpio); in cs43130_i2c_probe()
2546 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); in cs43130_i2c_probe()
2550 devid = cirrus_read_device_id(cs43130->regmap, CS43130_DEVID_AB); in cs43130_i2c_probe()
2553 dev_err(cs43130->dev, "Failed to read device ID: %d\n", ret); in cs43130_i2c_probe()
2564 dev_err(cs43130->dev, in cs43130_i2c_probe()
2568 ret = -ENODEV; in cs43130_i2c_probe()
2572 cs43130->dev_id = devid; in cs43130_i2c_probe()
2573 ret = regmap_read(cs43130->regmap, CS43130_REV_ID, ®); in cs43130_i2c_probe()
2575 dev_err(cs43130->dev, "Get Revision ID failed\n"); in cs43130_i2c_probe()
2579 dev_info(cs43130->dev, in cs43130_i2c_probe()
2583 mutex_init(&cs43130->clk_mutex); in cs43130_i2c_probe()
2585 init_completion(&cs43130->xtal_rdy); in cs43130_i2c_probe()
2586 init_completion(&cs43130->pll_rdy); in cs43130_i2c_probe()
2587 init_completion(&cs43130->hpload_evt); in cs43130_i2c_probe()
2589 if (!client->irq) { in cs43130_i2c_probe()
2590 dev_dbg(cs43130->dev, "IRQ not found, will poll instead\n"); in cs43130_i2c_probe()
2591 cs43130->has_irq_line = 0; in cs43130_i2c_probe()
2593 ret = devm_request_threaded_irq(cs43130->dev, client->irq, in cs43130_i2c_probe()
2598 dev_err(cs43130->dev, "Failed to request IRQ: %d\n", ret); in cs43130_i2c_probe()
2601 cs43130->has_irq_line = 1; in cs43130_i2c_probe()
2604 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; in cs43130_i2c_probe()
2606 pm_runtime_set_autosuspend_delay(cs43130->dev, 100); in cs43130_i2c_probe()
2607 pm_runtime_use_autosuspend(cs43130->dev); in cs43130_i2c_probe()
2608 pm_runtime_set_active(cs43130->dev); in cs43130_i2c_probe()
2609 pm_runtime_enable(cs43130->dev); in cs43130_i2c_probe()
2611 switch (cs43130->dev_id) { in cs43130_i2c_probe()
2622 ret = devm_snd_soc_register_component(cs43130->dev, component_driver, in cs43130_i2c_probe()
2625 dev_err(cs43130->dev, in cs43130_i2c_probe()
2630 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, in cs43130_i2c_probe()
2632 regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG, in cs43130_i2c_probe()
2638 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_i2c_probe()
2640 regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies), in cs43130_i2c_probe()
2641 cs43130->supplies); in cs43130_i2c_probe()
2650 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_i2c_remove()
2651 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_i2c_remove()
2655 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_i2c_remove()
2659 if (cs43130->dc_meas) { in cs43130_i2c_remove()
2660 cancel_work_sync(&cs43130->work); in cs43130_i2c_remove()
2661 flush_workqueue(cs43130->wq); in cs43130_i2c_remove()
2663 device_remove_file(cs43130->dev, &dev_attr_hpload_dc_l); in cs43130_i2c_remove()
2664 device_remove_file(cs43130->dev, &dev_attr_hpload_dc_r); in cs43130_i2c_remove()
2665 device_remove_file(cs43130->dev, &dev_attr_hpload_ac_l); in cs43130_i2c_remove()
2666 device_remove_file(cs43130->dev, &dev_attr_hpload_ac_r); in cs43130_i2c_remove()
2669 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_i2c_remove()
2671 pm_runtime_disable(cs43130->dev); in cs43130_i2c_remove()
2672 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_i2c_remove()
2679 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_runtime_suspend()
2680 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_runtime_suspend()
2684 regcache_cache_only(cs43130->regmap, true); in cs43130_runtime_suspend()
2685 regcache_mark_dirty(cs43130->regmap); in cs43130_runtime_suspend()
2687 gpiod_set_value_cansleep(cs43130->reset_gpio, 0); in cs43130_runtime_suspend()
2689 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_suspend()
2699 ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_resume()
2705 regcache_cache_only(cs43130->regmap, false); in cs43130_runtime_resume()
2707 gpiod_set_value_cansleep(cs43130->reset_gpio, 1); in cs43130_runtime_resume()
2711 ret = regcache_sync(cs43130->regmap); in cs43130_runtime_resume()
2717 if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) in cs43130_runtime_resume()
2718 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1, in cs43130_runtime_resume()
2723 regcache_cache_only(cs43130->regmap, true); in cs43130_runtime_resume()
2724 regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies); in cs43130_runtime_resume()