Lines Matching +full:0 +full:x3f
47 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
48 { 7, 0xDF }, /* r07 - Power Ctl 2 */
49 { 8, 0x3F }, /* r08 - Power Ctl 3 */
50 { 9, 0x50 }, /* r09 - Charge Pump Freq */
51 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
52 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
53 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
54 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
55 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
56 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
57 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
58 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
59 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
60 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
61 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
62 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
63 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
64 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
65 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
66 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
67 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
68 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
69 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
70 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
71 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
72 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
73 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
74 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
75 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
76 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
77 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
78 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
79 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
80 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
81 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
82 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
83 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
84 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
85 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
86 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
87 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
88 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
89 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
90 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
91 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
92 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
93 { 52, 0x18 }, /* r34 - Mixer Ctl */
94 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
95 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
96 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
97 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
98 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
99 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
100 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
101 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
102 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
103 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
104 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
105 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
106 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
107 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
108 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
109 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
110 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
111 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
112 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
113 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
114 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
115 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
116 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
117 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
118 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
119 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
120 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
121 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
122 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
123 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
124 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
125 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
126 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
127 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
128 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
129 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
130 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
131 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
132 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
133 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
134 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
135 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
136 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
162 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
163 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
166 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
168 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
170 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
172 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
175 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
176 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
216 CS42L73_NGCAB, 0,
222 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
252 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
278 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
294 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
295 0x41, 0x4B, hpaloa_tlv),
298 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
301 CS42L73_MICBPREPGABVOL, 0, 0x34,
302 0x24, micpga_tlv),
308 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
312 0, 0x34, 0xE4, hl_tlv),
315 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
318 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
321 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
324 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
331 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
332 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
339 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
340 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
341 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
342 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
345 0),
347 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
348 0),
349 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
350 0x3F, 0),
353 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
355 0),
363 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
364 0x3F, 0),
365 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
366 0x3F, 0),
367 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
369 6, 1, 0),
376 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
377 0x3F, 0),
378 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
379 0x3F, 0),
380 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
387 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
388 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
389 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
390 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
392 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
395 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
396 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
402 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
406 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
409 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
412 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
415 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
419 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
422 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
425 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
428 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
432 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
435 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
438 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
441 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
445 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
448 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
451 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
454 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
458 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
460 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
462 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
464 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
467 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
469 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
471 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
473 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
492 pr_err("Invalid event = 0x%x\n", event); in cs42l73_spklo_spk_amp_event()
494 return 0; in cs42l73_spklo_spk_amp_event()
509 pr_err("Invalid event = 0x%x\n", event); in cs42l73_ear_amp_event()
511 return 0; in cs42l73_ear_amp_event()
527 pr_err("Invalid event = 0x%x\n", event); in cs42l73_hp_amp_event()
529 return 0; in cs42l73_hp_amp_event()
538 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
540 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
542 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
544 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
546 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
548 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
550 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
553 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
554 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
556 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
557 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
565 0, 0, input_left_mixer,
569 0, 0, input_right_mixer,
572 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
573 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
574 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
575 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
576 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
578 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
579 CS42L73_PWRCTL2, 0, 1),
580 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
581 CS42L73_PWRCTL2, 0, 1),
582 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
583 CS42L73_PWRCTL2, 0, 1),
585 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
587 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
589 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
592 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
595 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
596 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
597 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
598 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
601 0, 0, &esl_xsp_mixer),
604 0, 0, &esl_asp_mixer),
607 0, 0, &spk_asp_mixer),
610 0, 0, &spk_xsp_mixer),
612 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
613 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
614 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
615 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
617 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
789 /* MCLK, Sample Rate, xMMCC[5:0] */
790 {5644800, 11025, 0x30},
791 {5644800, 22050, 0x20},
792 {5644800, 44100, 0x10},
794 {6000000, 8000, 0x39},
795 {6000000, 11025, 0x33},
796 {6000000, 12000, 0x31},
797 {6000000, 16000, 0x29},
798 {6000000, 22050, 0x23},
799 {6000000, 24000, 0x21},
800 {6000000, 32000, 0x19},
801 {6000000, 44100, 0x13},
802 {6000000, 48000, 0x11},
804 {6144000, 8000, 0x38},
805 {6144000, 12000, 0x30},
806 {6144000, 16000, 0x28},
807 {6144000, 24000, 0x20},
808 {6144000, 32000, 0x18},
809 {6144000, 48000, 0x10},
811 {6500000, 8000, 0x3C},
812 {6500000, 11025, 0x35},
813 {6500000, 12000, 0x34},
814 {6500000, 16000, 0x2C},
815 {6500000, 22050, 0x25},
816 {6500000, 24000, 0x24},
817 {6500000, 32000, 0x1C},
818 {6500000, 44100, 0x15},
819 {6500000, 48000, 0x14},
821 {6400000, 8000, 0x3E},
822 {6400000, 11025, 0x37},
823 {6400000, 12000, 0x36},
824 {6400000, 16000, 0x2E},
825 {6400000, 22050, 0x27},
826 {6400000, 24000, 0x26},
827 {6400000, 32000, 0x1E},
828 {6400000, 44100, 0x17},
829 {6400000, 48000, 0x16},
839 {5644800, 1, 0}, /* 5644800 */
840 {6000000, 1, 0}, /* 6000000 */
841 {6144000, 1, 0}, /* 6144000 */
856 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) { in cs42l73_get_mclkx_coeff()
867 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) { in cs42l73_get_mclk_coeff()
882 u32 mclk = 0; in cs42l73_set_mclk()
883 u8 dmmcc = 0; in cs42l73_set_mclk()
887 if (mclkx_coeff < 0) in cs42l73_set_mclk()
905 return 0; in cs42l73_set_mclk()
923 if ((cs42l73_set_mclk(dai, freq)) < 0) { in cs42l73_set_sysclk()
931 return 0; in cs42l73_set_sysclk()
1005 return 0; in cs42l73_set_dai_fmt()
1016 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) { in cs42l73_get_xspfs_coeff()
1020 return 0; /* 0 = Don't know */ in cs42l73_get_xspfs_coeff()
1025 u8 spfs = 0; in cs42l73_update_asrc()
1027 if (srate > 0) in cs42l73_update_asrc()
1032 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs); in cs42l73_update_asrc()
1035 snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2); in cs42l73_update_asrc()
1038 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4); in cs42l73_update_asrc()
1061 if (mclk_coeff < 0) in cs42l73_pcm_hw_params()
1065 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", in cs42l73_pcm_hw_params()
1069 priv->config[id].mmcc &= 0xC0; in cs42l73_pcm_hw_params()
1071 priv->config[id].spc &= 0xFC; in cs42l73_pcm_hw_params()
1079 priv->config[id].spc &= 0xFC; in cs42l73_pcm_hw_params()
1090 return 0; in cs42l73_pcm_hw_params()
1100 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0); in cs42l73_set_bias_level()
1101 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0); in cs42l73_set_bias_level()
1117 if (cs42l73->shutdwn_delay > 0) { in cs42l73_set_bias_level()
1119 cs42l73->shutdwn_delay = 0; in cs42l73_set_bias_level()
1128 return 0; in cs42l73_set_bias_level()
1148 snd_pcm_hw_constraint_list(substream->runtime, 0, in cs42l73_pcm_startup()
1151 return 0; in cs42l73_pcm_startup()
1241 cs42l73->mclk = 0; in cs42l73_probe()
1243 return 0; in cs42l73_probe()
1305 "chgfreq", &val32) >= 0) in cs42l73_i2c_probe()
1309 "reset-gpio", 0); in cs42l73_i2c_probe()
1320 if (ret < 0) { in cs42l73_i2c_probe()
1325 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0); in cs42l73_i2c_probe()
1331 if (devid < 0) { in cs42l73_i2c_probe()
1346 if (ret < 0) { in cs42l73_i2c_probe()
1352 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); in cs42l73_i2c_probe()
1357 if (ret < 0) in cs42l73_i2c_probe()
1360 return 0; in cs42l73_i2c_probe()
1363 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0); in cs42l73_i2c_probe()