20 #define INTH_R5F_STATUS_OFFSET     0x040
21 #define INTH_R5F_CLEAR_OFFSET      0x048
22 #define INTH_R5F_MASK_SET_OFFSET   0x050
23 #define INTH_R5F_MASK_CLEAR_OFFSET 0x054
25 #define BF_REARM_FREE_MARK_OFFSET 0x344
26 #define BF_REARM_FULL_MARK_OFFSET 0x348
30 #define SRC_RBUF_0_RDADDR_OFFSET 0x500
31 #define SRC_RBUF_1_RDADDR_OFFSET 0x518
32 #define SRC_RBUF_2_RDADDR_OFFSET 0x530
33 #define SRC_RBUF_3_RDADDR_OFFSET 0x548
34 #define SRC_RBUF_4_RDADDR_OFFSET 0x560
35 #define SRC_RBUF_5_RDADDR_OFFSET 0x578
36 #define SRC_RBUF_6_RDADDR_OFFSET 0x590
39 #define SRC_RBUF_0_WRADDR_OFFSET 0x504
40 #define SRC_RBUF_1_WRADDR_OFFSET 0x51c
41 #define SRC_RBUF_2_WRADDR_OFFSET 0x534
42 #define SRC_RBUF_3_WRADDR_OFFSET 0x54c
43 #define SRC_RBUF_4_WRADDR_OFFSET 0x564
44 #define SRC_RBUF_5_WRADDR_OFFSET 0x57c
45 #define SRC_RBUF_6_WRADDR_OFFSET 0x594
48 #define SRC_RBUF_0_BASEADDR_OFFSET 0x508
49 #define SRC_RBUF_1_BASEADDR_OFFSET 0x520
50 #define SRC_RBUF_2_BASEADDR_OFFSET 0x538
51 #define SRC_RBUF_3_BASEADDR_OFFSET 0x550
52 #define SRC_RBUF_4_BASEADDR_OFFSET 0x568
53 #define SRC_RBUF_5_BASEADDR_OFFSET 0x580
54 #define SRC_RBUF_6_BASEADDR_OFFSET 0x598
57 #define SRC_RBUF_0_ENDADDR_OFFSET 0x50c
58 #define SRC_RBUF_1_ENDADDR_OFFSET 0x524
59 #define SRC_RBUF_2_ENDADDR_OFFSET 0x53c
60 #define SRC_RBUF_3_ENDADDR_OFFSET 0x554
61 #define SRC_RBUF_4_ENDADDR_OFFSET 0x56c
62 #define SRC_RBUF_5_ENDADDR_OFFSET 0x584
63 #define SRC_RBUF_6_ENDADDR_OFFSET 0x59c
66 #define SRC_RBUF_0_FREE_MARK_OFFSET 0x510
67 #define SRC_RBUF_1_FREE_MARK_OFFSET 0x528
68 #define SRC_RBUF_2_FREE_MARK_OFFSET 0x540
69 #define SRC_RBUF_3_FREE_MARK_OFFSET 0x558
70 #define SRC_RBUF_4_FREE_MARK_OFFSET 0x570
71 #define SRC_RBUF_5_FREE_MARK_OFFSET 0x588
72 #define SRC_RBUF_6_FREE_MARK_OFFSET 0x5a0
75 #define DST_RBUF_0_RDADDR_OFFSET 0x5c0
76 #define DST_RBUF_1_RDADDR_OFFSET 0x5d8
77 #define DST_RBUF_2_RDADDR_OFFSET 0x5f0
78 #define DST_RBUF_3_RDADDR_OFFSET 0x608
79 #define DST_RBUF_4_RDADDR_OFFSET 0x620
80 #define DST_RBUF_5_RDADDR_OFFSET 0x638
83 #define DST_RBUF_0_WRADDR_OFFSET 0x5c4
84 #define DST_RBUF_1_WRADDR_OFFSET 0x5dc
85 #define DST_RBUF_2_WRADDR_OFFSET 0x5f4
86 #define DST_RBUF_3_WRADDR_OFFSET 0x60c
87 #define DST_RBUF_4_WRADDR_OFFSET 0x624
88 #define DST_RBUF_5_WRADDR_OFFSET 0x63c
91 #define DST_RBUF_0_BASEADDR_OFFSET 0x5c8
92 #define DST_RBUF_1_BASEADDR_OFFSET 0x5e0
93 #define DST_RBUF_2_BASEADDR_OFFSET 0x5f8
94 #define DST_RBUF_3_BASEADDR_OFFSET 0x610
95 #define DST_RBUF_4_BASEADDR_OFFSET 0x628
96 #define DST_RBUF_5_BASEADDR_OFFSET 0x640
99 #define DST_RBUF_0_ENDADDR_OFFSET 0x5cc
100 #define DST_RBUF_1_ENDADDR_OFFSET 0x5e4
101 #define DST_RBUF_2_ENDADDR_OFFSET 0x5fc
102 #define DST_RBUF_3_ENDADDR_OFFSET 0x614
103 #define DST_RBUF_4_ENDADDR_OFFSET 0x62c
104 #define DST_RBUF_5_ENDADDR_OFFSET 0x644
107 #define DST_RBUF_0_FULL_MARK_OFFSET 0x5d0
108 #define DST_RBUF_1_FULL_MARK_OFFSET 0x5e8
109 #define DST_RBUF_2_FULL_MARK_OFFSET 0x600
110 #define DST_RBUF_3_FULL_MARK_OFFSET 0x618
111 #define DST_RBUF_4_FULL_MARK_OFFSET 0x630
112 #define DST_RBUF_5_FULL_MARK_OFFSET 0x648
117 #define ESR0_STATUS_OFFSET 0x900
118 #define ESR1_STATUS_OFFSET 0x918
119 #define ESR2_STATUS_OFFSET 0x930
120 #define ESR3_STATUS_OFFSET 0x948
121 #define ESR4_STATUS_OFFSET 0x960
124 #define ESR0_STATUS_CLR_OFFSET 0x908
125 #define ESR1_STATUS_CLR_OFFSET 0x920
126 #define ESR2_STATUS_CLR_OFFSET 0x938
127 #define ESR3_STATUS_CLR_OFFSET 0x950
128 #define ESR4_STATUS_CLR_OFFSET 0x968
131 #define ESR0_MASK_STATUS_OFFSET 0x90c
132 #define ESR1_MASK_STATUS_OFFSET 0x924
133 #define ESR2_MASK_STATUS_OFFSET 0x93c
134 #define ESR3_MASK_STATUS_OFFSET 0x954
135 #define ESR4_MASK_STATUS_OFFSET 0x96c
138 #define ESR0_MASK_SET_OFFSET 0x910
139 #define ESR1_MASK_SET_OFFSET 0x928
140 #define ESR2_MASK_SET_OFFSET 0x940
141 #define ESR3_MASK_SET_OFFSET 0x958
142 #define ESR4_MASK_SET_OFFSET 0x970
145 #define ESR0_MASK_CLR_OFFSET 0x914
146 #define ESR1_MASK_CLR_OFFSET 0x92c
147 #define ESR2_MASK_CLR_OFFSET 0x944
148 #define ESR3_MASK_CLR_OFFSET 0x95c
149 #define ESR4_MASK_CLR_OFFSET 0x974
152 #define R5F_ESR0_SHIFT  0    /* esr0 = fifo underflow */
171 #define PERIOD_BYTES_MIN 0x100
182 	.period_bytes_max = 0x10000,
192 	.buffer_bytes_max = 4 * 0x8000,
202 	return snd_soc_dai_get_dma_data(snd_soc_rtd_to_cpu(soc_runtime, 0), substream);  in cygnus_dai_get_dma_data()
250 	int status = 0;  in configure_ringbuf_regs()
259 		case 0:  in configure_ringbuf_regs()
260 			*p_rbuf = RINGBUF_REG_PLAYBACK(0);  in configure_ringbuf_regs()
278 		case 0:  in configure_ringbuf_regs()
279 			*p_rbuf = RINGBUF_REG_CAPTURE(0);  in configure_ringbuf_regs()
352 	dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "%s on port %d\n", __func__, aio->portnum);  in disable_intr()
372 	int ret = 0;  in cygnus_pcm_trigger()
421  *  0x1	I2S0_out port caused interrupt
422  *  0x2	I2S1_out port caused interrupt
423  *  0x4	I2S2_out port caused interrupt
424  *  0x8	SPDIF_out port caused interrupt
447 	for (port = 0; port < CYGNUS_MAX_PLAYBACK_PORTS; port++) {  in handle_playback_irq()
459 				"Underrun: esr0=0x%x, esr1=0x%x esr3=0x%x\n",  in handle_playback_irq()
485  *  0x1	I2S0_in port caused interrupt
486  *  0x2	I2S1_in port caused interrupt
487  *  0x4	I2S2_in port caused interrupt
508 	for (port = 0; port < CYGNUS_MAX_CAPTURE_PORTS; port++) {  in handle_capture_irq()
520 				"Overflow: esr2=0x%x\n", esr_status2);  in handle_capture_irq()
543 	 *  0		ESR0 (playback FIFO interrupt)  in cygnus_dma_irq()
583 	dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);  in cygnus_pcm_open()
587 	ret = snd_pcm_hw_constraint_step(runtime, 0,  in cygnus_pcm_open()
589 	if (ret < 0)  in cygnus_pcm_open()
592 	ret = snd_pcm_hw_constraint_step(runtime, 0,  in cygnus_pcm_open()
594 	if (ret < 0)  in cygnus_pcm_open()
605 	return 0;  in cygnus_pcm_open()
616 	dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "%s  port %d\n", __func__, aio->portnum);  in cygnus_pcm_close()
624 		dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "freed  port %d\n", aio->portnum);  in cygnus_pcm_close()
626 	return 0;  in cygnus_pcm_close()
641 	dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "%s port %d\n", __func__, aio->portnum);  in cygnus_pcm_prepare()
646 	dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "%s (buf_size %lu) (period_size %lu)\n",  in cygnus_pcm_prepare()
655 	is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1 : 0;  in cygnus_pcm_prepare()
660 	return 0;  in cygnus_pcm_prepare()
667 	unsigned int res = 0, cur = 0, base = 0;  in cygnus_pcm_pointer()
688 	res = (cur & 0x7fffffff) - (base & 0x7fffffff);  in cygnus_pcm_pointer()
707 	return 0;  in cygnus_dma_new()
734 					     NULL, 0);  in cygnus_soc_platform_register()
740 	return 0;  in cygnus_soc_platform_register()
745 	return 0;  in cygnus_soc_platform_unregister()