296  * @gclk: generic clock
306 	struct clk				*gclk;  member
476 	/* GCLK is enabled by runtime PM. */  in mchp_spdifrx_hw_params()
477 	clk_disable_unprepare(dev->gclk);  in mchp_spdifrx_hw_params()
479 	ret = clk_set_min_rate(dev->gclk, params_rate(params) *  in mchp_spdifrx_hw_params()
483 			"unable to set gclk min rate: rate %u * ratio %u + 1\n",  in mchp_spdifrx_hw_params()
486 		clk_prepare_enable(dev->gclk);  in mchp_spdifrx_hw_params()
489 	ret = clk_prepare_enable(dev->gclk);  in mchp_spdifrx_hw_params()
491 		dev_err(dev->dev, "unable to enable gclk: %d\n", ret);  in mchp_spdifrx_hw_params()
495 	dev_dbg(dev->dev, "GCLK range min set to %d\n",  in mchp_spdifrx_hw_params()
716 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_ulock_get()
754 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_badf_get()
856 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_rate_get()
873 	rate = clk_get_rate(dev->gclk);  in mchp_spdifrx_rate_get()
1044 	clk_disable_unprepare(spdifrx->gclk);  in mchp_spdifrx_runtime_suspend()
1059 	ret = clk_prepare_enable(spdifrx->gclk);  in mchp_spdifrx_runtime_resume()
1068 		clk_disable_unprepare(spdifrx->gclk);  in mchp_spdifrx_runtime_resume()
1126 	dev->gclk = devm_clk_get(&pdev->dev, "gclk");  in mchp_spdifrx_probe()
1127 	if (IS_ERR(dev->gclk)) {  in mchp_spdifrx_probe()
1128 		err = PTR_ERR(dev->gclk);  in mchp_spdifrx_probe()
1135 	 * Signal control need a valid rate on gclk. hw_params() configures  in mchp_spdifrx_probe()
1138 	 * gclk at a valid rate, here, in initialization, to simplify the  in mchp_spdifrx_probe()
1141 	clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);  in mchp_spdifrx_probe()