Lines Matching +full:0 +full:x1240000

11 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_DEVICE_ID 0x15E2
13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK	0x00010001
15 #define ACP_PGFSM_CNTL_POWER_ON_MASK	0x01
16 #define ACP_PGFSM_CNTL_POWER_OFF_MASK	0x00
17 #define ACP_PGFSM_STATUS_MASK		0x03
18 #define ACP_POWERED_ON			0x00
19 #define ACP_POWER_ON_IN_PROGRESS	0x01
20 #define ACP_POWERED_OFF			0x02
21 #define ACP_POWER_OFF_IN_PROGRESS	0x03
23 #define ACP_ERR_INTR_MASK	0x20000000
24 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
27 #define	ACP5x_REG_START	0x1240000
28 #define	ACP5x_REG_END	0x1250200
29 #define ACP5x_I2STDM_REG_START	0x1242400
30 #define ACP5x_I2STDM_REG_END	0x1242410
31 #define ACP5x_HS_TDM_REG_START	0x1242814
32 #define ACP5x_HS_TDM_REG_END	0x1242824
33 #define I2S_MODE 0
44 #define ACP_SRAM_PTE_OFFSET	0x02050000
45 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
46 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
47 #define ACP_SRAM_HS_PB_PTE_OFFSET	0x200
48 #define ACP_SRAM_HS_CP_PTE_OFFSET	0x300
49 #define PAGE_SIZE_4K_ENABLE 0x2
50 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
51 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
52 #define I2S_HS_TX_MEM_WINDOW_START	0x4040000
53 #define I2S_HS_RX_MEM_WINDOW_START	0x4060000
55 #define SP_PB_FIFO_ADDR_OFFSET		0x500
56 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
57 #define HS_PB_FIFO_ADDR_OFFSET		0x900
58 #define HS_CAPT_FIFO_ADDR_OFFSET	0xB00
70 #define FIFO_SIZE 0x100
71 #define DMA_SIZE 0x40
72 #define FRM_LEN 0x100
75 #define I2S_MASTER_MODE_DISABLE 0
82 #define TDM_DISABLE 0
83 #define ACP5x_ITER_IRER_SAMP_LEN_MASK	0x38
215 	mclkgen.bits.i2stdm_master_mode = 0x1;  in acp5x_set_i2s_clk()
217 		mclkgen.bits.i2stdm_format_mode = 0x01;  in acp5x_set_i2s_clk()
219 		mclkgen.bits.i2stdm_format_mode = 0x00;  in acp5x_set_i2s_clk()