Lines Matching +full:0 +full:x1240000

10 #define I2S_SP_INSTANCE                 0x01
11 #define I2S_BT_INSTANCE                 0x02
14 #define TDM_DISABLE 0
17 #define ACP3x_PHY_BASE_ADDRESS 0x1240000
18 #define	ACP3x_I2S_MODE	0
19 #define	ACP3x_REG_START	0x1240000
20 #define	ACP3x_REG_END	0x1250200
21 #define ACP3x_I2STDM_REG_START	0x1242400
22 #define ACP3x_I2STDM_REG_END	0x1242410
23 #define ACP3x_BT_TDM_REG_START	0x1242800
24 #define ACP3x_BT_TDM_REG_END	0x1242810
25 #define I2S_MODE	0x04
31 #define ACP3x_POWER_ON 0x00
32 #define ACP3x_POWER_ON_IN_PROGRESS 0x01
33 #define ACP3x_POWER_OFF 0x02
34 #define ACP3x_POWER_OFF_IN_PROGRESS 0x03
35 #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK	0x00010001
37 #define ACP_SRAM_PTE_OFFSET	0x02050000
38 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
39 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
40 #define ACP_SRAM_BT_PB_PTE_OFFSET	0x200
41 #define ACP_SRAM_BT_CP_PTE_OFFSET	0x300
42 #define PAGE_SIZE_4K_ENABLE 0x2
43 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
44 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
45 #define I2S_BT_TX_MEM_WINDOW_START	0x4040000
46 #define I2S_BT_RX_MEM_WINDOW_START	0x4060000
48 #define SP_PB_FIFO_ADDR_OFFSET		0x500
49 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
50 #define BT_PB_FIFO_ADDR_OFFSET		0x900
51 #define BT_CAPT_FIFO_ADDR_OFFSET	0xB00
63 #define FIFO_SIZE 0x100
64 #define DMA_SIZE 0x40
65 #define FRM_LEN 0x100
67 #define SLOT_WIDTH_8 0x08
68 #define SLOT_WIDTH_16 0x10
69 #define SLOT_WIDTH_24 0x18
70 #define SLOT_WIDTH_32 0x20
71 #define ACP_PGFSM_CNTL_POWER_ON_MASK	0x01
72 #define ACP_PGFSM_CNTL_POWER_OFF_MASK	0x00
73 #define ACP_PGFSM_STATUS_MASK		0x03
74 #define ACP_POWERED_ON			0x00
75 #define ACP_POWER_ON_IN_PROGRESS	0x01
76 #define ACP_POWERED_OFF			0x02
77 #define ACP_POWER_OFF_IN_PROGRESS	0x03
79 #define ACP3x_ITER_IRER_SAMP_LEN_MASK	0x38
80 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF