amd/acp/acp63.c

29 #define CLK_PLL_PWR_REQ_N0		0X0006C2C0
30 #define CLK_SPLL_FIELD_2_N0		0X0006C114
31 #define CLK_PLL_REQ_N0			0X0006C0DC
32 #define CLK_DFSBYPASS_CONTR		0X0006C2C8
33 #define CLK_DFS_CNTL_N0			0X0006C1A4
36 #define PLL_AUTO_START_REQ		BIT(0)
40 #define CLK0_DIVIDER			0X30
53 	.offset = 0,
57 	.irq_reg_offset = 0x1a00,
58 	.scratch_reg_offset = 0x12800,
59 	.sram_pte_offset = 0x03802800,
167 	smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x14E8, NULL);  in acp63_i2s_master_clock_generate()
172 	clk_pll.bits.fb_mult_int = 0x31;  in acp63_i2s_master_clock_generate()
173 	clk_pll.bits.pll_spine_div = 0;  in acp63_i2s_master_clock_generate()
174 	clk_pll.bits.gb_mult_frac = 0x26E9;  in acp63_i2s_master_clock_generate()
193 	return 0;  in acp63_i2s_master_clock_generate()
259 	return 0;  in acp63_audio_probe()
298 	return 0;  in acp63_pcm_resume()