40 	writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);  in acp_dmic_prepare()
41 	dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);  in acp_dmic_prepare()
43 	writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);  in acp_dmic_prepare()
56 	writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);  in acp_dmic_prepare()
57 	writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);  in acp_dmic_prepare()
58 	writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);  in acp_dmic_prepare()
59 	writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);  in acp_dmic_prepare()
76 		dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);  in acp_dmic_dai_trigger()
78 			writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);  in acp_dmic_dai_trigger()
79 			writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);  in acp_dmic_dai_trigger()
82 		ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,  in acp_dmic_dai_trigger()
89 		dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);  in acp_dmic_dai_trigger()
91 			writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);  in acp_dmic_dai_trigger()
92 			writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);  in acp_dmic_dai_trigger()
96 		ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,  in acp_dmic_dai_trigger()
137 	writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);  in acp_dmic_hwparams()
138 	writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);  in acp_dmic_hwparams()