Lines Matching +full:0 +full:x11000

11 #define G2_FIFO 0xa05f688c
12 #define SPU_MEMORY_BASE 0xA0800000
13 #define ARM_RESET_REGISTER 0xA0702C00
14 #define SPU_REGISTER_BASE 0xA0700000
17 #define AICA_CONTROL_POINT 0xA0810000
18 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
19 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
22 #define AICA_CMD_KICK 0x80000000
23 #define AICA_CMD_NONE 0
30 #define SM_16BIT	0
34 #define AICA_BUFFER_SIZE 0x8000
35 #define AICA_PERIOD_SIZE 0x800
38 #define AICA_CHANNEL0_OFFSET 0x11000
39 #define AICA_CHANNEL1_OFFSET 0x21000
40 #define CHANNEL_OFFSET 0x10000
52 	uint32_t vol;		/* Volume 0-255         */
53 	uint32_t pan;		/* Pan 0-255            */