214 	u32 wcreg;    /* cached write control register value */  member
254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
511 	writel(rme96->wcreg | RME96_WCR_PD,  in snd_rme96_reset_dac()
513 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_reset_dac()
519 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +  in snd_rme96_getmontracks()
520 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);  in snd_rme96_getmontracks()
528 		rme96->wcreg |= RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
530 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
533 		rme96->wcreg |= RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
535 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
537 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setmontracks()
544 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +  in snd_rme96_getattenuation()
545 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);  in snd_rme96_getattenuation()
554 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
558 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
562 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
566 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
572 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setattenuation()
644 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_getrate()
653 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +  in snd_rme96_playback_getrate()
654 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);  in snd_rme96_playback_getrate()
668 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;  in snd_rme96_playback_getrate()
677 	ds = rme96->wcreg & RME96_WCR_DS;  in snd_rme96_playback_setrate()
680 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
681 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
685 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
686 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
690 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
691 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
695 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
696 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
700 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
701 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
705 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
706 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
712 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||  in snd_rme96_playback_setrate()
713 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))  in snd_rme96_playback_setrate()
719 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setrate()
773 		rme96->wcreg &= ~RME96_WCR_MASTER;  in snd_rme96_setclockmode()
778 		rme96->wcreg |= RME96_WCR_MASTER;  in snd_rme96_setclockmode()
783 		rme96->wcreg |= RME96_WCR_MASTER;   in snd_rme96_setclockmode()
789 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setclockmode()
800 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :  in snd_rme96_getclockmode()
812 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
816 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
820 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
832 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
861 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setinputtype()
871 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +  in snd_rme96_getinputtype()
872 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);  in snd_rme96_getinputtype()
889 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;  in snd_rme96_setframelog()
892 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;  in snd_rme96_setframelog()
902 		rme96->wcreg &= ~RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
905 		rme96->wcreg |= RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
910 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setformat()
919 		rme96->wcreg &= ~RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
922 		rme96->wcreg |= RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
927 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_capture_setformat()
937 		rme96->wcreg &= ~RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
940 		rme96->wcreg |= RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
946 	rme96->wcreg &= ~RME96_WCR_IDIS;  in snd_rme96_set_period_properties()
947 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_set_period_properties()
966 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_hw_params()
998 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {  in snd_rme96_playback_hw_params()
999 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_playback_hw_params()
1000 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_hw_params()
1089 		rme96->wcreg |= RME96_WCR_START;  in snd_rme96_trigger()
1091 		rme96->wcreg &= ~RME96_WCR_START;  in snd_rme96_trigger()
1093 		rme96->wcreg |= RME96_WCR_START_2;  in snd_rme96_trigger()
1095 		rme96->wcreg &= ~RME96_WCR_START_2;  in snd_rme96_trigger()
1096 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_trigger()
1170 	rme96->wcreg &= ~RME96_WCR_ADAT;  in snd_rme96_playback_spdif_open()
1171 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_spdif_open()
1176 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_spdif_open()
1240 	rme96->wcreg |= RME96_WCR_ADAT;  in snd_rme96_playback_adat_open()
1241 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_adat_open()
1246 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_adat_open()
1309 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;  in snd_rme96_playback_close()
1638 	rme96->wcreg =  in snd_rme96_create()
1646 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_create()
1696 	if (rme96->wcreg & RME96_WCR_IDIS) {  in snd_rme96_proc_read()
1699 	} else if (rme96->wcreg & RME96_WCR_ISEL) {  in snd_rme96_proc_read()
1733 	if (rme96->wcreg & RME96_WCR_MODE24_2) {  in snd_rme96_proc_read()
1740 	if (rme96->wcreg & RME96_WCR_SEL) {  in snd_rme96_proc_read()
1747 	if (rme96->wcreg & RME96_WCR_MODE24) {  in snd_rme96_proc_read()
1754 	} else if (rme96->wcreg & RME96_WCR_MASTER) {  in snd_rme96_proc_read()
1763 	if (rme96->wcreg & RME96_WCR_PRO) {  in snd_rme96_proc_read()
1768 	if (rme96->wcreg & RME96_WCR_EMP) {  in snd_rme96_proc_read()
1773 	if (rme96->wcreg & RME96_WCR_DOLBY) {  in snd_rme96_proc_read()
1830 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;  in snd_rme96_get_loopback_control()
1843 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;  in snd_rme96_put_loopback_control()
1844 	change = val != rme96->wcreg;  in snd_rme96_put_loopback_control()
1845 	rme96->wcreg = val;  in snd_rme96_put_loopback_control()
2143 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_control_spdif_stream_put()
2144 	rme96->wcreg |= val;  in snd_rme96_control_spdif_stream_put()
2145 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_control_spdif_stream_put()