Lines Matching +full:0 +full:x007fffff
23 0,
24 0x400,
25 0x401,
26 0x402,
27 0x403,
28 0x404,
29 0x405,
30 0x406,
31 0x407,
32 0x408,
33 0x409,
34 0x40a,
35 0x40b,
36 0x40c,
38 0x410,
39 0x411,
40 0x412,
41 0x413,
42 0x414,
43 0x415,
44 0x416,
46 0x420,
47 0x430,
48 0x431,
49 0x432,
50 0x433,
51 0x434,
52 0x440
74 for (i = 0; i != len; ++i) in lx_dsp_reg_readbuf()
92 for (i = 0; i != len; ++i) in lx_dsp_reg_writebuf()
98 0x04,
99 0x40,
100 0x44,
101 0x48,
102 0x4c,
103 0x50,
104 0x54,
105 0x58,
106 0x5c,
107 0x64,
108 0x68,
109 0x6C
138 #define Reg_CSM_MR 0x00000002
139 #define Reg_CSM_MC 0x00000001
145 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for
158 offset in the status registers: 0 means that the return value may be
159 different from 0, and must be read
167 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
171 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
173 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
175 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
179 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
181 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
185 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
189 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
191 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
193 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
197 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
205 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
212 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; in lx_message_init()
217 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); in lx_message_init()
220 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); in lx_message_init()
236 for (i = 0; i != rmh->cmd_len; ++i) in lx_message_dump()
239 for (i = 0; i != rmh->stat_len; ++i) in lx_message_dump()
273 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { in lx_message_send_atomic()
275 if (rmh->dsp_stat == 0) in lx_message_send_atomic()
278 reg = 0; in lx_message_send_atomic()
287 if ((reg & ERROR_VALUE) == 0) { in lx_message_send_atomic()
298 lx_dsp_reg_write(chip, eReg_CSM, 0); in lx_message_send_atomic()
333 u16 ret = 0; in lx_dsp_get_clock_frequency()
334 u32 freq_raw = 0; in lx_dsp_get_clock_frequency()
335 u32 freq = 0; in lx_dsp_get_clock_frequency()
336 u32 frequency = 0; in lx_dsp_get_clock_frequency()
343 if (ret == 0) { in lx_dsp_get_clock_frequency()
344 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; in lx_dsp_get_clock_frequency()
349 frequency = 0; /* unknown */ in lx_dsp_get_clock_frequency()
367 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; in lx_dsp_get_mac()
368 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; in lx_dsp_get_mac()
371 chip->mac_address[5] = ((u8 *)(&maclsb))[0]; in lx_dsp_get_mac()
374 chip->mac_address[2] = ((u8 *)(&macmsb))[0]; in lx_dsp_get_mac()
376 chip->mac_address[0] = ((u8 *)(&macmsb))[2]; in lx_dsp_get_mac()
378 return 0; in lx_dsp_get_mac()
389 chip->rmh.cmd[0] |= gran; in lx_dsp_set_granularity()
415 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
429 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_allocate()
430 chip->rmh.cmd[0] |= channels; in lx_pipe_allocate()
435 if (err != 0) in lx_pipe_allocate()
449 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_release()
465 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); in lx_buffer_ask()
468 *r_needed = 0; in lx_buffer_ask()
469 *r_freed = 0; in lx_buffer_ask()
474 chip->rmh.cmd[0] |= pipe_cmd; in lx_buffer_ask()
480 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { in lx_buffer_ask()
488 == 0) in lx_buffer_ask()
496 for (i = 0; i < MAX_STREAM_BUFFER && i < chip->rmh.stat_len; in lx_buffer_ask()
517 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_stop()
533 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_toggle_state()
547 if (err < 0) in lx_pipe_start()
557 int err = 0; in lx_pipe_pause()
560 if (err < 0) in lx_pipe_pause()
578 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_sample_count()
583 if (err != 0) in lx_pipe_sample_count()
587 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) in lx_pipe_sample_count()
604 chip->rmh.cmd[0] |= pipe_cmd; in lx_pipe_state()
608 if (err != 0) in lx_pipe_state()
611 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; in lx_pipe_state()
624 for (i = 0; i != 50; ++i) { in lx_pipe_wait_for_state()
628 if (err < 0) in lx_pipe_wait_for_state()
632 return 0; in lx_pipe_wait_for_state()
660 chip->rmh.cmd[0] |= pipe_cmd; in lx_stream_set_state()
661 chip->rmh.cmd[0] |= state; in lx_stream_set_state()
679 chip->rmh.cmd[0] |= pipe_cmd; in lx_stream_set_format()
683 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); in lx_stream_set_format()
687 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); in lx_stream_set_format()
689 chip->rmh.cmd[0] |= channels-1; in lx_stream_set_format()
706 chip->rmh.cmd[0] |= pipe_cmd; in lx_stream_state()
710 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; in lx_stream_state()
725 chip->rmh.cmd[0] |= pipe_cmd; in lx_stream_sample_position()
729 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) in lx_stream_sample_position()
748 chip->rmh.cmd[0] |= pipe_cmd; in lx_buffer_give()
749 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ in lx_buffer_give()
759 chip->rmh.cmd[0] |= BF_64BITS_ADR; in lx_buffer_give()
764 if (err == 0) { in lx_buffer_give()
765 *r_buffer_index = chip->rmh.stat[0]; in lx_buffer_give()
795 chip->rmh.cmd[0] |= pipe_cmd; in lx_buffer_free()
796 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the in lx_buffer_free()
801 if (err == 0) in lx_buffer_free()
802 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; in lx_buffer_free()
817 chip->rmh.cmd[0] |= pipe_cmd; in lx_buffer_cancel()
818 chip->rmh.cmd[0] |= buffer_index; in lx_buffer_cancel()
836 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; in lx_level_unmute()
841 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); in lx_level_unmute()
844 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ in lx_level_unmute()
847 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], in lx_level_unmute()
857 0x00000109, /* -90.308dB */
858 0x0000083B, /* -72.247dB */
859 0x000020C4, /* -60.205dB */
860 0x00008273, /* -48.030dB */
861 0x00020756, /* -36.005dB */
862 0x00040C37, /* -30.001dB */
863 0x00081385, /* -24.002dB */
864 0x00101D3F, /* -18.000dB */
865 0x0016C310, /* -15.000dB */
866 0x002026F2, /* -12.001dB */
867 0x002D6A86, /* -9.000dB */
868 0x004026E6, /* -6.004dB */
869 0x005A9DF6, /* -3.000dB */
870 0x0065AC8B, /* -2.000dB */
871 0x00721481, /* -1.000dB */
872 0x007FFFFF, /* FS */
878 int err = 0; in lx_level_peaks()
882 for (i = 0; i < channels; i += 4) { in lx_level_peaks()
886 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); in lx_level_peaks()
890 if (err == 0) { in lx_level_peaks()
891 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; in lx_level_peaks()
892 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; in lx_level_peaks()
893 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; in lx_level_peaks()
894 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; in lx_level_peaks()
896 s0 = s1 = s2 = s3 = 0; in lx_level_peaks()
898 r_levels[0] = s0; in lx_level_peaks()
911 #define PCX_IRQ_NONE 0
943 return 0; in lx_interrupt_ack()
973 * Stat[0] general status in lx_interrupt_handle_async_events()
984 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; in lx_interrupt_handle_async_events()
985 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; in lx_interrupt_handle_async_events()
987 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; in lx_interrupt_handle_async_events()
990 if (err < 0) in lx_interrupt_handle_async_events()
1024 0 : pos + 1; in lx_interrupt_request_new_buffer()
1027 u32 buf_hi = 0; in lx_interrupt_request_new_buffer()
1028 u32 buf_lo = 0; in lx_interrupt_request_new_buffer()
1029 u32 buffer_index = 0; in lx_interrupt_request_new_buffer()
1038 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); in lx_interrupt_request_new_buffer()
1043 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, in lx_interrupt_request_new_buffer()
1046 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n", in lx_interrupt_request_new_buffer()
1106 u64 notified_in_pipe_mask = 0; in lx_threaded_irq()
1107 u64 notified_out_pipe_mask = 0; in lx_threaded_irq()
1125 if (err < 0) in lx_threaded_irq()
1137 if (err < 0) in lx_threaded_irq()
1172 lx_irq_set(chip, 0); in lx_irq_disable()