22 #define CM9825_VERB_SET_HPF_1 0x781
23 #define CM9825_VERB_SET_HPF_2 0x785
24 #define CM9825_VERB_SET_PLL 0x7a0
25 #define CM9825_VERB_SET_NEG 0x7a1
26 #define CM9825_VERB_SET_ADCL 0x7a2
27 #define CM9825_VERB_SET_DACL 0x7a3
28 #define CM9825_VERB_SET_MBIAS 0x7a4
29 #define CM9825_VERB_SET_VNEG 0x7a8
30 #define CM9825_VERB_SET_D2S 0x7a9
31 #define CM9825_VERB_SET_DACTRL 0x7aa
32 #define CM9825_VERB_SET_PDNEG 0x7ac
33 #define CM9825_VERB_SET_VDO 0x7ad
34 #define CM9825_VERB_SET_CDALR 0x7b0
35 #define CM9825_VERB_SET_MTCBA 0x7b1
36 #define CM9825_VERB_SET_OTP 0x7b2
37 #define CM9825_VERB_SET_OCP 0x7b3
38 #define CM9825_VERB_SET_GAD 0x7b4
39 #define CM9825_VERB_SET_TMOD 0x7b5
40 #define CM9825_VERB_SET_SNR 0x7b6
55 	{0x43, CM9825_VERB_SET_D2S, 0x62},	/* depop */
56 	{0x43, CM9825_VERB_SET_PLL, 0x01},	/* PLL set */
57 	{0x43, CM9825_VERB_SET_NEG, 0xc2},	/* NEG set */
58 	{0x43, CM9825_VERB_SET_ADCL, 0x00},	/* ADC */
59 	{0x43, CM9825_VERB_SET_DACL, 0x02},	/* DACL */
60 	{0x43, CM9825_VERB_SET_VNEG, 0x50},	/* VOL NEG */
61 	{0x43, CM9825_VERB_SET_MBIAS, 0x00},	/* MBIAS */
62 	{0x43, CM9825_VERB_SET_PDNEG, 0x04},	/* SEL OSC */
63 	{0x43, CM9825_VERB_SET_CDALR, 0xf6},	/* Class D */
64 	{0x43, CM9825_VERB_SET_OTP, 0xcd},	/* OTP set */
70 	{0x34, AC_VERB_SET_EAPD_BTLENABLE, 0x02},	/* EAPD set */
71 	{0x43, CM9825_VERB_SET_SNR, 0x30},	/* SNR set */
72 	{0x43, CM9825_VERB_SET_PLL, 0x00},	/* PLL set */
73 	{0x43, CM9825_VERB_SET_ADCL, 0x00},	/* ADC */
74 	{0x43, CM9825_VERB_SET_DACL, 0x02},	/* DACL */
75 	{0x43, CM9825_VERB_SET_MBIAS, 0x00},	/* MBIAS */
76 	{0x43, CM9825_VERB_SET_VNEG, 0x56},	/* VOL NEG */
77 	{0x43, CM9825_VERB_SET_D2S, 0x62},	/* depop */
78 	{0x43, CM9825_VERB_SET_DACTRL, 0x00},	/* DACTRL set */
79 	{0x43, CM9825_VERB_SET_PDNEG, 0x0c},	/* SEL OSC */
80 	{0x43, CM9825_VERB_SET_VDO, 0x80},	/* VDO set */
81 	{0x43, CM9825_VERB_SET_CDALR, 0xf4},	/* Class D */
82 	{0x43, CM9825_VERB_SET_OTP, 0xcd},	/* OTP set */
83 	{0x43, CM9825_VERB_SET_MTCBA, 0x61},	/* SR set */
84 	{0x43, CM9825_VERB_SET_OCP, 0x33},	/* OTP set */
85 	{0x43, CM9825_VERB_SET_GAD, 0x07},	/* ADC -3db */
86 	{0x43, CM9825_VERB_SET_TMOD, 0x26},	/* Class D clk */
87 	{0x3C, AC_VERB_SET_AMP_GAIN_MUTE |
88 		AC_AMP_SET_OUTPUT | AC_AMP_SET_RIGHT, 0x2d},	/* Gain set */
89 	{0x3C, AC_VERB_SET_AMP_GAIN_MUTE |
90 		AC_AMP_SET_OUTPUT | AC_AMP_SET_LEFT, 0x2d},	/* Gain set */
91 	{0x43, CM9825_VERB_SET_HPF_1, 0x40},	/* HPF set */
92 	{0x43, CM9825_VERB_SET_HPF_2, 0x40},	/* HPF set */
97 	{0x42, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00},	/* PIN off */
98 	{0x43, CM9825_VERB_SET_ADCL, 0x88},	/* ADC */
99 	{0x43, CM9825_VERB_SET_DACL, 0xaa},	/* DACL */
100 	{0x43, CM9825_VERB_SET_MBIAS, 0x10},	/* MBIAS */
101 	{0x43, CM9825_VERB_SET_D2S, 0xf2},	/* depop */
102 	{0x43, CM9825_VERB_SET_DACTRL, 0x00},	/* DACTRL set */
103 	{0x43, CM9825_VERB_SET_VDO, 0xc4},	/* VDO set */
108 	{0x43, CM9825_VERB_SET_ADCL, 0x00},	/* ADC */
109 	{0x43, CM9825_VERB_SET_DACL, 0x56},	/* DACL */
110 	{0x43, CM9825_VERB_SET_MBIAS, 0x00},	/* MBIAS */
111 	{0x43, CM9825_VERB_SET_D2S, 0x62},	/* depop */
112 	{0x43, CM9825_VERB_SET_DACTRL, 0xe0},	/* DACTRL set */
113 	{0x43, CM9825_VERB_SET_VDO, 0x80},	/* VDO set */
114 	{0x42, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40},	/* PIN on */
123 	hda_nid_t hp_pin = spec->gen.autocfg.hp_pins[0];  in cm9825_unsol_hp_delayed()
125 	int err = 0;  in cm9825_unsol_hp_delayed()
129 	codec_dbg(spec->codec, "hp_jack_plugin %d, hp_pin 0x%X\n",  in cm9825_unsol_hp_delayed()
134 		    snd_hda_codec_write(spec->codec, 0x42, 0,  in cm9825_unsol_hp_delayed()
135 					AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);  in cm9825_unsol_hp_delayed()
147 		jack->block_report = 0;  in cm9825_unsol_hp_delayed()
161 	codec_dbg(spec->codec, "cb->nid 0x%X\n", cb->nid);  in hp_callback()
173 	hda_nid_t hp_pin = spec->gen.autocfg.hp_pins[0];  in cm9825_setup_unsol()
183 	return 0;  in cm9825_init()
202 	return 0;  in cm9825_suspend()
208 	hda_nid_t hp_pin = 0;  in cm9825_resume()
213 	    snd_hda_codec_write(spec->codec, 0x42, 0,  in cm9825_resume()
214 				AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);  in cm9825_resume()
222 	hp_pin = spec->gen.autocfg.hp_pins[0];  in cm9825_resume()
225 	codec_dbg(spec->codec, "hp_jack_plugin %d, hp_pin 0x%X\n",  in cm9825_resume()
230 		    snd_hda_codec_write(spec->codec, 0x42, 0,  in cm9825_resume()
231 					AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);  in cm9825_resume()
240 	hda_call_check_power_status(codec, 0x01);  in cm9825_resume()
242 	return 0;  in cm9825_resume()
284 	err = snd_hda_parse_pin_defcfg(codec, cfg, NULL, 0);  in patch_cm9825()
285 	if (err < 0)  in patch_cm9825()
288 	if (err < 0)  in patch_cm9825()
293 	return 0;  in patch_cm9825()
318 	err = snd_hda_parse_pin_defcfg(codec, cfg, NULL, 0);  in patch_cmi9880()
319 	if (err < 0)  in patch_cmi9880()
322 	if (err < 0)  in patch_cmi9880()
325 	return 0;  in patch_cmi9880()
347 	/* mask NID 0x10 from the playback volume selection;  in patch_cmi8888()
350 	spec->gen.out_vol_mask = (1ULL << 0x10);  in patch_cmi8888()
352 	err = snd_hda_parse_pin_defcfg(codec, cfg, NULL, 0);  in patch_cmi8888()
353 	if (err < 0)  in patch_cmi8888()
356 	if (err < 0)  in patch_cmi8888()
359 	if (get_defcfg_device(snd_hda_codec_get_pincfg(codec, 0x10)) ==  in patch_cmi8888()
363 					 0x10, 0, HDA_OUTPUT);  in patch_cmi8888()
370 	return 0;  in patch_cmi8888()
381 	HDA_CODEC_ENTRY(0x13f68888, "CMI8888", patch_cmi8888),
382 	HDA_CODEC_ENTRY(0x13f69880, "CMI9880", patch_cmi9880),
383 	HDA_CODEC_ENTRY(0x434d4980, "CMI9880", patch_cmi9880),
384 	HDA_CODEC_ENTRY(0x13f69825, "CM9825", patch_cm9825),