Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
1 // SPDX-License-Identifier: GPL-2.0-only
48 #define SRCCTL_STATE 0x00000007
49 #define SRCCTL_BM 0x00000008
50 #define SRCCTL_RSR 0x00000030
51 #define SRCCTL_SF 0x000001C0
52 #define SRCCTL_WR 0x00000200
53 #define SRCCTL_PM 0x00000400
54 #define SRCCTL_ROM 0x00001800
55 #define SRCCTL_VO 0x00002000
56 #define SRCCTL_ST 0x00004000
57 #define SRCCTL_IE 0x00008000
58 #define SRCCTL_ILSZ 0x000F0000
59 #define SRCCTL_BP 0x00100000
61 #define SRCCCR_CISZ 0x000007FF
62 #define SRCCCR_CWA 0x001FF800
63 #define SRCCCR_D 0x00200000
64 #define SRCCCR_RS 0x01C00000
65 #define SRCCCR_NAL 0x3E000000
66 #define SRCCCR_RA 0xC0000000
68 #define SRCCA_CA 0x0FFFFFFF
69 #define SRCCA_RS 0xE0000000
71 #define SRCSA_SA 0x0FFFFFFF
73 #define SRCLA_LA 0x0FFFFFFF
76 * Fixed-point value in 8.24 format for parameter channel */
77 #define MPRLH_PITCH 0xFFFFFFFF
88 u16 czbfs:1; /* Clear Z-Buffers */
128 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000
162 return -ENOMEM; in src_get_rsc_ctrl_blk()
166 return 0; in src_get_rsc_ctrl_blk()
173 return 0; in src_put_rsc_ctrl_blk()
180 set_field(&ctl->ctl, SRCCTL_STATE, state); in src_set_state()
181 ctl->dirty.bf.ctl = 1; in src_set_state()
182 return 0; in src_set_state()
189 set_field(&ctl->ctl, SRCCTL_BM, bm); in src_set_bm()
190 ctl->dirty.bf.ctl = 1; in src_set_bm()
191 return 0; in src_set_bm()
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr); in src_set_rsr()
199 ctl->dirty.bf.ctl = 1; in src_set_rsr()
200 return 0; in src_set_rsr()
207 set_field(&ctl->ctl, SRCCTL_SF, sf); in src_set_sf()
208 ctl->dirty.bf.ctl = 1; in src_set_sf()
209 return 0; in src_set_sf()
216 set_field(&ctl->ctl, SRCCTL_WR, wr); in src_set_wr()
217 ctl->dirty.bf.ctl = 1; in src_set_wr()
218 return 0; in src_set_wr()
225 set_field(&ctl->ctl, SRCCTL_PM, pm); in src_set_pm()
226 ctl->dirty.bf.ctl = 1; in src_set_pm()
227 return 0; in src_set_pm()
234 set_field(&ctl->ctl, SRCCTL_ROM, rom); in src_set_rom()
235 ctl->dirty.bf.ctl = 1; in src_set_rom()
236 return 0; in src_set_rom()
243 set_field(&ctl->ctl, SRCCTL_VO, vo); in src_set_vo()
244 ctl->dirty.bf.ctl = 1; in src_set_vo()
245 return 0; in src_set_vo()
252 set_field(&ctl->ctl, SRCCTL_ST, st); in src_set_st()
253 ctl->dirty.bf.ctl = 1; in src_set_st()
254 return 0; in src_set_st()
261 set_field(&ctl->ctl, SRCCTL_IE, ie); in src_set_ie()
262 ctl->dirty.bf.ctl = 1; in src_set_ie()
263 return 0; in src_set_ie()
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz); in src_set_ilsz()
271 ctl->dirty.bf.ctl = 1; in src_set_ilsz()
272 return 0; in src_set_ilsz()
279 set_field(&ctl->ctl, SRCCTL_BP, bp); in src_set_bp()
280 ctl->dirty.bf.ctl = 1; in src_set_bp()
281 return 0; in src_set_bp()
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz); in src_set_cisz()
289 ctl->dirty.bf.ccr = 1; in src_set_cisz()
290 return 0; in src_set_cisz()
297 set_field(&ctl->ca, SRCCA_CA, ca); in src_set_ca()
298 ctl->dirty.bf.ca = 1; in src_set_ca()
299 return 0; in src_set_ca()
306 set_field(&ctl->sa, SRCSA_SA, sa); in src_set_sa()
307 ctl->dirty.bf.sa = 1; in src_set_sa()
308 return 0; in src_set_sa()
315 set_field(&ctl->la, SRCLA_LA, la); in src_set_la()
316 ctl->dirty.bf.la = 1; in src_set_la()
317 return 0; in src_set_la()
324 set_field(&ctl->mpr, MPRLH_PITCH, pitch); in src_set_pitch()
325 ctl->dirty.bf.mpr = 1; in src_set_pitch()
326 return 0; in src_set_pitch()
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); in src_set_clear_zbufs()
332 return 0; in src_set_clear_zbufs()
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); in src_set_dirty()
338 return 0; in src_set_dirty()
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); in src_set_dirty_all()
344 return 0; in src_set_dirty_all()
350 #define AR_PARAM_SRC_OFFSET 0x60
355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; in src_param_pitch_mixer()
364 if (ctl->dirty.bf.czbfs) { in src_commit_write()
365 /* Clear Z-Buffer registers */ in src_commit_write()
366 for (i = 0; i < 8; i++) in src_commit_write()
367 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0); in src_commit_write()
369 for (i = 0; i < 4; i++) in src_commit_write()
370 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0); in src_commit_write()
372 for (i = 0; i < 8; i++) in src_commit_write()
373 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0); in src_commit_write()
375 ctl->dirty.bf.czbfs = 0; in src_commit_write()
377 if (ctl->dirty.bf.mpr) { in src_commit_write()
383 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr); in src_commit_write()
384 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3); in src_commit_write()
385 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0); in src_commit_write()
386 ctl->dirty.bf.mpr = 0; in src_commit_write()
388 if (ctl->dirty.bf.sa) { in src_commit_write()
389 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa); in src_commit_write()
390 ctl->dirty.bf.sa = 0; in src_commit_write()
392 if (ctl->dirty.bf.la) { in src_commit_write()
393 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la); in src_commit_write()
394 ctl->dirty.bf.la = 0; in src_commit_write()
396 if (ctl->dirty.bf.ca) { in src_commit_write()
397 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca); in src_commit_write()
398 ctl->dirty.bf.ca = 0; in src_commit_write()
402 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0); in src_commit_write()
404 if (ctl->dirty.bf.ccr) { in src_commit_write()
405 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr); in src_commit_write()
406 ctl->dirty.bf.ccr = 0; in src_commit_write()
408 if (ctl->dirty.bf.ctl) { in src_commit_write()
409 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl); in src_commit_write()
410 ctl->dirty.bf.ctl = 0; in src_commit_write()
413 return 0; in src_commit_write()
420 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100); in src_get_ca()
421 ctl->dirty.bf.ca = 0; in src_get_ca()
423 return get_field(ctl->ca, SRCCA_CA); in src_get_ca()
428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; in src_get_dirty()
433 return 0x20; in src_dirty_conj_mask()
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4)); in src_mgr_enbs_src()
439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; in src_mgr_enbs_src()
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); in src_mgr_enbs_src()
441 return 0; in src_mgr_enbs_src()
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); in src_mgr_enb_src()
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); in src_mgr_enb_src()
448 return 0; in src_mgr_enb_src()
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); in src_mgr_dsb_src()
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); in src_mgr_dsb_src()
455 return 0; in src_mgr_dsb_src()
464 if (ctl->dirty.bf.enbsa) { in src_mgr_commit_write()
467 } while (ret & 0x1); in src_mgr_commit_write()
468 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa); in src_mgr_commit_write()
469 ctl->dirty.bf.enbsa = 0; in src_mgr_commit_write()
471 for (i = 0; i < 8; i++) { in src_mgr_commit_write()
472 if ((ctl->dirty.data & (0x1 << i))) { in src_mgr_commit_write()
473 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]); in src_mgr_commit_write()
474 ctl->dirty.data &= ~(0x1 << i); in src_mgr_commit_write()
478 return 0; in src_mgr_commit_write()
488 return -ENOMEM; in src_mgr_get_ctrl_blk()
492 return 0; in src_mgr_get_ctrl_blk()
499 return 0; in src_mgr_put_ctrl_blk()
509 return -ENOMEM; in srcimp_mgr_get_ctrl_blk()
513 return 0; in srcimp_mgr_get_ctrl_blk()
520 return 0; in srcimp_mgr_put_ctrl_blk()
527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot); in srcimp_mgr_set_imaparc()
528 ctl->dirty.bf.srcimap = 1; in srcimp_mgr_set_imaparc()
529 return 0; in srcimp_mgr_set_imaparc()
536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user); in srcimp_mgr_set_imapuser()
537 ctl->dirty.bf.srcimap = 1; in srcimp_mgr_set_imapuser()
538 return 0; in srcimp_mgr_set_imapuser()
545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next); in srcimp_mgr_set_imapnxt()
546 ctl->dirty.bf.srcimap = 1; in srcimp_mgr_set_imapnxt()
547 return 0; in srcimp_mgr_set_imapnxt()
552 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr; in srcimp_mgr_set_imapaddr()
553 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1; in srcimp_mgr_set_imapaddr()
554 return 0; in srcimp_mgr_set_imapaddr()
561 if (ctl->dirty.bf.srcimap) { in srcimp_mgr_commit_write()
562 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100, in srcimp_mgr_commit_write()
563 ctl->srcimap.srcaim); in srcimp_mgr_commit_write()
564 ctl->dirty.bf.srcimap = 0; in srcimp_mgr_commit_write()
567 return 0; in srcimp_mgr_commit_write()
574 #define AMOPLO_M 0x00000003
575 #define AMOPLO_IV 0x00000004
576 #define AMOPLO_X 0x0003FFF0
577 #define AMOPLO_Y 0xFFFC0000
579 #define AMOPHI_SADR 0x000000FF
580 #define AMOPHI_SE 0x80000000
603 set_field(&ctl->amoplo, AMOPLO_M, mode); in amixer_set_mode()
604 ctl->dirty.bf.amoplo = 1; in amixer_set_mode()
605 return 0; in amixer_set_mode()
612 set_field(&ctl->amoplo, AMOPLO_IV, iv); in amixer_set_iv()
613 ctl->dirty.bf.amoplo = 1; in amixer_set_iv()
614 return 0; in amixer_set_iv()
621 set_field(&ctl->amoplo, AMOPLO_X, x); in amixer_set_x()
622 ctl->dirty.bf.amoplo = 1; in amixer_set_x()
623 return 0; in amixer_set_x()
630 set_field(&ctl->amoplo, AMOPLO_Y, y); in amixer_set_y()
631 ctl->dirty.bf.amoplo = 1; in amixer_set_y()
632 return 0; in amixer_set_y()
639 set_field(&ctl->amophi, AMOPHI_SADR, sadr); in amixer_set_sadr()
640 ctl->dirty.bf.amophi = 1; in amixer_set_sadr()
641 return 0; in amixer_set_sadr()
648 set_field(&ctl->amophi, AMOPHI_SE, se); in amixer_set_se()
649 ctl->dirty.bf.amophi = 1; in amixer_set_se()
650 return 0; in amixer_set_se()
655 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); in amixer_set_dirty()
656 return 0; in amixer_set_dirty()
661 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); in amixer_set_dirty_all()
662 return 0; in amixer_set_dirty_all()
669 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { in amixer_commit_write()
670 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo); in amixer_commit_write()
671 ctl->dirty.bf.amoplo = 0; in amixer_commit_write()
672 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi); in amixer_commit_write()
673 ctl->dirty.bf.amophi = 0; in amixer_commit_write()
676 return 0; in amixer_commit_write()
683 return get_field(ctl->amoplo, AMOPLO_Y); in amixer_get_y()
688 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; in amixer_get_dirty()
698 return -ENOMEM; in amixer_rsc_get_ctrl_blk()
702 return 0; in amixer_rsc_get_ctrl_blk()
709 return 0; in amixer_rsc_put_ctrl_blk()
716 return 0; in amixer_mgr_get_ctrl_blk()
721 return 0; in amixer_mgr_put_ctrl_blk()
729 #define SRTCTL_SRCO 0x000000FF
730 #define SRTCTL_SRCM 0x0000FF00
731 #define SRTCTL_RSR 0x00030000
732 #define SRTCTL_DRAT 0x00300000
733 #define SRTCTL_EC 0x01000000
734 #define SRTCTL_ET 0x10000000
752 #define AIM_ARC 0x00000FFF
753 #define AIM_NXT 0x007F0000
761 #define ATXCTL_EN 0x00000001
762 #define ATXCTL_MODE 0x00000010
763 #define ATXCTL_CD 0x00000020
764 #define ATXCTL_RAW 0x00000100
765 #define ATXCTL_MT 0x00000200
766 #define ATXCTL_NUC 0x00003000
767 #define ATXCTL_BEN 0x00010000
768 #define ATXCTL_BMUX 0x00700000
769 #define ATXCTL_B24 0x01000000
770 #define ATXCTL_CPF 0x02000000
771 #define ATXCTL_RIV 0x10000000
772 #define ATXCTL_LIV 0x20000000
773 #define ATXCTL_RSAT 0x40000000
774 #define ATXCTL_LSAT 0x80000000
793 #define ARXCTL_EN 0x00000001
818 set_field(&ctl->srt, SRTCTL_SRCO, src); in dai_srt_set_srco()
819 ctl->dirty.bf.srt = 1; in dai_srt_set_srco()
820 return 0; in dai_srt_set_srco()
827 set_field(&ctl->srt, SRTCTL_SRCM, src); in dai_srt_set_srcm()
828 ctl->dirty.bf.srt = 1; in dai_srt_set_srcm()
829 return 0; in dai_srt_set_srcm()
836 set_field(&ctl->srt, SRTCTL_RSR, rsr); in dai_srt_set_rsr()
837 ctl->dirty.bf.srt = 1; in dai_srt_set_rsr()
838 return 0; in dai_srt_set_rsr()
845 set_field(&ctl->srt, SRTCTL_DRAT, drat); in dai_srt_set_drat()
846 ctl->dirty.bf.srt = 1; in dai_srt_set_drat()
847 return 0; in dai_srt_set_drat()
854 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0); in dai_srt_set_ec()
855 ctl->dirty.bf.srt = 1; in dai_srt_set_ec()
856 return 0; in dai_srt_set_ec()
863 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0); in dai_srt_set_et()
864 ctl->dirty.bf.srt = 1; in dai_srt_set_et()
865 return 0; in dai_srt_set_et()
872 if (ctl->dirty.bf.srt) { in dai_commit_write()
873 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt); in dai_commit_write()
874 ctl->dirty.bf.srt = 0; in dai_commit_write()
877 return 0; in dai_commit_write()
887 return -ENOMEM; in dai_get_ctrl_blk()
891 return 0; in dai_get_ctrl_blk()
898 return 0; in dai_put_ctrl_blk()
903 ((struct dao_ctrl_blk *)blk)->atxcsl = spos; in dao_set_spos()
904 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1; in dao_set_spos()
905 return 0; in dao_set_spos()
912 if (ctl->dirty.bf.atxcsl) { in dao_commit_write()
915 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx, in dao_commit_write()
916 ctl->atxcsl); in dao_commit_write()
918 ctl->dirty.bf.atxcsl = 0; in dao_commit_write()
921 return 0; in dao_commit_write()
926 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl; in dao_get_spos()
927 return 0; in dao_get_spos()
937 return -ENOMEM; in dao_get_ctrl_blk()
941 return 0; in dao_get_ctrl_blk()
948 return 0; in dao_put_ctrl_blk()
955 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1); in daio_mgr_enb_dai()
956 ctl->dirty.bf.arxctl |= (0x1 << idx); in daio_mgr_enb_dai()
957 return 0; in daio_mgr_enb_dai()
964 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0); in daio_mgr_dsb_dai()
966 ctl->dirty.bf.arxctl |= (0x1 << idx); in daio_mgr_dsb_dai()
967 return 0; in daio_mgr_dsb_dai()
974 set_field(&ctl->txctl[idx], ATXCTL_EN, 1); in daio_mgr_enb_dao()
975 ctl->dirty.bf.atxctl |= (0x1 << idx); in daio_mgr_enb_dao()
976 return 0; in daio_mgr_enb_dao()
983 set_field(&ctl->txctl[idx], ATXCTL_EN, 0); in daio_mgr_dsb_dao()
984 ctl->dirty.bf.atxctl |= (0x1 << idx); in daio_mgr_dsb_dao()
985 return 0; in daio_mgr_dsb_dao()
994 switch ((conf & 0xf)) { in daio_mgr_dao_init()
996 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0); in daio_mgr_dao_init()
999 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1); in daio_mgr_dao_init()
1002 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2); in daio_mgr_dao_init()
1005 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3); in daio_mgr_dao_init()
1011 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7))); in daio_mgr_dao_init()
1012 /* Non-audio */ in daio_mgr_dao_init()
1013 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1); in daio_mgr_dao_init()
1014 /* Non-audio */ in daio_mgr_dao_init()
1015 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1); in daio_mgr_dao_init()
1016 set_field(&ctl->txctl[idx], ATXCTL_RAW, in daio_mgr_dao_init()
1017 ((conf >> 3) & 0x1) ? 0 : 0); in daio_mgr_dao_init()
1018 ctl->dirty.bf.atxctl |= (0x1 << idx); in daio_mgr_dao_init()
1023 return 0; in daio_mgr_dao_init()
1030 set_field(&ctl->daoimap.aim, AIM_ARC, slot); in daio_mgr_set_imaparc()
1031 ctl->dirty.bf.daoimap = 1; in daio_mgr_set_imaparc()
1032 return 0; in daio_mgr_set_imaparc()
1039 set_field(&ctl->daoimap.aim, AIM_NXT, next); in daio_mgr_set_imapnxt()
1040 ctl->dirty.bf.daoimap = 1; in daio_mgr_set_imapnxt()
1041 return 0; in daio_mgr_set_imapnxt()
1046 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr; in daio_mgr_set_imapaddr()
1047 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1; in daio_mgr_set_imapaddr()
1048 return 0; in daio_mgr_set_imapaddr()
1057 for (i = 0; i < 8; i++) { in daio_mgr_commit_write()
1058 if ((ctl->dirty.bf.atxctl & (0x1 << i))) { in daio_mgr_commit_write()
1059 data = ctl->txctl[i]; in daio_mgr_commit_write()
1060 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); in daio_mgr_commit_write()
1061 ctl->dirty.bf.atxctl &= ~(0x1 << i); in daio_mgr_commit_write()
1064 if ((ctl->dirty.bf.arxctl & (0x1 << i))) { in daio_mgr_commit_write()
1065 data = ctl->rxctl[i]; in daio_mgr_commit_write()
1066 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); in daio_mgr_commit_write()
1067 ctl->dirty.bf.arxctl &= ~(0x1 << i); in daio_mgr_commit_write()
1071 if (ctl->dirty.bf.daoimap) { in daio_mgr_commit_write()
1072 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4, in daio_mgr_commit_write()
1073 ctl->daoimap.aim); in daio_mgr_commit_write()
1074 ctl->dirty.bf.daoimap = 0; in daio_mgr_commit_write()
1077 return 0; in daio_mgr_commit_write()
1088 return -ENOMEM; in daio_mgr_get_ctrl_blk()
1090 for (i = 0; i < 8; i++) { in daio_mgr_get_ctrl_blk()
1091 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i)); in daio_mgr_get_ctrl_blk()
1092 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i)); in daio_mgr_get_ctrl_blk()
1097 return 0; in daio_mgr_get_ctrl_blk()
1104 return 0; in daio_mgr_put_ctrl_blk()
1110 hw_write_20kx(hw, GIE, enable ? IT_INT : 0); in set_timer_irq()
1111 return 0; in set_timer_irq()
1119 return 0; in set_timer_tick()
1152 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */ in hw_daio_init()
1153 if (1 == info->msr) { in hw_daio_init()
1154 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101); in hw_daio_init()
1155 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101); in hw_daio_init()
1156 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); in hw_daio_init()
1157 } else if (2 == info->msr) { in hw_daio_init()
1158 if (hw->model != CTSB1270) { in hw_daio_init()
1159 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111); in hw_daio_init()
1162 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111); in hw_daio_init()
1165 * EA [0] - Enabled in hw_daio_init()
1166 * RTA [4:5] - 96kHz in hw_daio_init()
1167 * EB [8] - Enabled in hw_daio_init()
1168 * RTB [12:13] - 96kHz in hw_daio_init()
1169 * EC [16] - Enabled in hw_daio_init()
1170 * RTC [20:21] - 96kHz in hw_daio_init()
1171 * ED [24] - Enabled in hw_daio_init()
1172 * RTD [28:29] - 96kHz */ in hw_daio_init()
1173 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111); in hw_daio_init()
1174 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); in hw_daio_init()
1175 } else if ((4 == info->msr) && (hw->model == CTSB1270)) { in hw_daio_init()
1176 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111); in hw_daio_init()
1177 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121); in hw_daio_init()
1178 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0); in hw_daio_init()
1180 dev_alert(hw->card->dev, in hw_daio_init()
1182 return -EINVAL; in hw_daio_init()
1185 for (i = 0; i < 8; i++) { in hw_daio_init()
1191 data = 0x1001001; in hw_daio_init()
1193 data = 0x1000001; in hw_daio_init()
1195 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data); in hw_daio_init()
1196 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data); in hw_daio_init()
1203 * Category code = 0x12 (Digital Signal Mixer), in hw_daio_init()
1204 * Mode = 0, Emph = 0, Copy Permitted, AN = 0 in hw_daio_init()
1206 * and the Professional Use bit is 0. */ in hw_daio_init()
1208 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i), in hw_daio_init()
1209 0x02109204); /* Default to 48kHz */ in hw_daio_init()
1211 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B); in hw_daio_init()
1215 data = 0x11; in hw_daio_init()
1216 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data); in hw_daio_init()
1217 if (2 == info->msr) { in hw_daio_init()
1219 data |= 0x1000; in hw_daio_init()
1220 } else if (4 == info->msr) { in hw_daio_init()
1222 data |= 0x2000; in hw_daio_init()
1224 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data); in hw_daio_init()
1228 return 0; in hw_daio_init()
1239 if ((~0UL) == info->vm_pgt_phys) { in hw_trn_init()
1240 dev_alert(hw->card->dev, in hw_trn_init()
1242 return -1; in hw_trn_init()
1245 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */ in hw_trn_init()
1246 ptp_phys_low = (u32)info->vm_pgt_phys; in hw_trn_init()
1247 ptp_phys_high = upper_32_bits(info->vm_pgt_phys); in hw_trn_init()
1251 for (i = 0; i < 64; i++) { in hw_trn_init()
1258 hw_write_20kx(hw, TRANSPORT_CTL, 0x03); in hw_trn_init()
1259 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01); in hw_trn_init()
1262 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03)); in hw_trn_init()
1264 return 0; in hw_trn_init()
1268 #define GCTL_AIE 0x00000001
1269 #define GCTL_UAA 0x00000002
1270 #define GCTL_DPC 0x00000004
1271 #define GCTL_DBP 0x00000008
1272 #define GCTL_ABP 0x00000010
1273 #define GCTL_TBP 0x00000020
1274 #define GCTL_SBP 0x00000040
1275 #define GCTL_FBP 0x00000080
1276 #define GCTL_ME 0x00000100
1277 #define GCTL_AID 0x00001000
1279 #define PLLCTL_SRC 0x00000007
1280 #define PLLCTL_SPE 0x00000008
1281 #define PLLCTL_RD 0x000000F0
1282 #define PLLCTL_FD 0x0001FF00
1283 #define PLLCTL_OD 0x00060000
1284 #define PLLCTL_B 0x00080000
1285 #define PLLCTL_AS 0x00100000
1286 #define PLLCTL_LF 0x03E00000
1287 #define PLLCTL_SPS 0x1C000000
1288 #define PLLCTL_AD 0x60000000
1290 #define PLLSTAT_CCS 0x00000007
1291 #define PLLSTAT_SPL 0x00000008
1292 #define PLLSTAT_CRD 0x000000F0
1293 #define PLLSTAT_CFD 0x0001FF00
1294 #define PLLSTAT_SL 0x00020000
1295 #define PLLSTAT_FAS 0x00040000
1296 #define PLLSTAT_B 0x00080000
1297 #define PLLSTAT_PD 0x00100000
1298 #define PLLSTAT_OCA 0x00200000
1299 #define PLLSTAT_NCA 0x00400000
1308 pllenb = 0xB; in hw_pll_init()
1310 pllctl = 0x20C00000; in hw_pll_init()
1311 set_field(&pllctl, PLLCTL_B, 0); in hw_pll_init()
1312 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4); in hw_pll_init()
1313 set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1); in hw_pll_init()
1318 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2); in hw_pll_init()
1322 for (i = 0; i < 1000; i++) { in hw_pll_init()
1346 dev_alert(hw->card->dev, in hw_pll_init()
1348 return -EBUSY; in hw_pll_init()
1351 return 0; in hw_pll_init()
1360 set_field(&gctl, GCTL_AIE, 0); in hw_auto_init()
1365 for (i = 0; i < 400000; i++) { in hw_auto_init()
1371 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n"); in hw_auto_init()
1372 return -EBUSY; in hw_auto_init()
1375 return 0; in hw_auto_init()
1380 #define CS4382_MC1 0x1
1381 #define CS4382_MC2 0x2
1382 #define CS4382_MC3 0x3
1383 #define CS4382_FC 0x4
1384 #define CS4382_IC 0x5
1385 #define CS4382_XC1 0x6
1386 #define CS4382_VCA1 0x7
1387 #define CS4382_VCB1 0x8
1388 #define CS4382_XC2 0x9
1389 #define CS4382_VCA2 0xA
1390 #define CS4382_VCB2 0xB
1391 #define CS4382_XC3 0xC
1392 #define CS4382_VCA3 0xD
1393 #define CS4382_VCB3 0xE
1394 #define CS4382_XC4 0xF
1395 #define CS4382_VCA4 0x10
1396 #define CS4382_VCB4 0x11
1397 #define CS4382_CREV 0x12
1400 #define STATE_LOCKED 0x00
1401 #define STATE_UNLOCKED 0xAA
1402 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1403 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1405 #define I2C_STATUS_DCM 0x00000001
1406 #define I2C_STATUS_BC 0x00000006
1407 #define I2C_STATUS_APD 0x00000008
1408 #define I2C_STATUS_AB 0x00010000
1409 #define I2C_STATUS_DR 0x00800000
1411 #define I2C_ADDRESS_PTAD 0x0000FFFF
1412 #define I2C_ADDRESS_SLAD 0x007F0000
1441 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4}; in hw20k2_i2c_unlock_full_access()
1445 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]); in hw20k2_i2c_unlock_full_access()
1450 return 0; in hw20k2_i2c_unlock_full_access()
1452 return -1; in hw20k2_i2c_unlock_full_access()
1461 return 0; in hw20k2_i2c_lock_chip()
1463 return -1; in hw20k2_i2c_lock_chip()
1474 if (err < 0) in hw20k2_i2c_init()
1477 hw20k2->addr_size = addr_size; in hw20k2_i2c_init()
1478 hw20k2->data_size = data_size; in hw20k2_i2c_init()
1479 hw20k2->dev_id = dev_id; in hw20k2_i2c_init()
1481 i2c_addr = 0; in hw20k2_i2c_init()
1492 return 0; in hw20k2_i2c_init()
1500 i2c_addr = 0; in hw20k2_i2c_uninit()
1501 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */ in hw20k2_i2c_uninit()
1507 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */ in hw20k2_i2c_uninit()
1516 int i = 0x400000; in hw20k2_i2c_wait_data_ready()
1521 } while ((!(ret & DATA_READY)) && --i); in hw20k2_i2c_wait_data_ready()
1533 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size); in hw20k2_i2c_read()
1536 return -1; in hw20k2_i2c_read()
1540 return -1; in hw20k2_i2c_read()
1543 hw_write_20kx(hw, I2C_IF_RDATA, 0); in hw20k2_i2c_read()
1545 return -1; in hw20k2_i2c_read()
1549 return 0; in hw20k2_i2c_read()
1555 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr; in hw20k2_i2c_write()
1561 (4 == (hw20k2->addr_size + hw20k2->data_size)) ? in hw20k2_i2c_write()
1562 0 : (hw20k2->addr_size + hw20k2->data_size)); in hw20k2_i2c_write()
1567 hw_write_20kx(hw, I2C_IF_WDATA, 0); in hw20k2_i2c_write()
1574 return 0; in hw20k2_i2c_write()
1581 data &= 0xFFFFFFFD; in hw_dac_stop()
1590 data |= 0x2; in hw_dac_start()
1606 struct regs_cs4382 cs_read = {0}; in hw_dac_init()
1608 .mode_control_1 = 0x00000001, /* Mode Control 1 */ in hw_dac_init()
1609 .mode_control_2 = 0x00000000, /* Mode Control 2 */ in hw_dac_init()
1610 .mode_control_3 = 0x00000084, /* Mode Control 3 */ in hw_dac_init()
1611 .filter_control = 0x00000000, /* Filter Control */ in hw_dac_init()
1612 .invert_control = 0x00000000, /* Invert Control */ in hw_dac_init()
1613 .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */ in hw_dac_init()
1614 .vol_control_A1 = 0x00000000, /* Vol Control A1 */ in hw_dac_init()
1615 .vol_control_B1 = 0x00000000, /* Vol Control B1 */ in hw_dac_init()
1616 .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */ in hw_dac_init()
1617 .vol_control_A2 = 0x00000000, /* Vol Control A2 */ in hw_dac_init()
1618 .vol_control_B2 = 0x00000000, /* Vol Control B2 */ in hw_dac_init()
1619 .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */ in hw_dac_init()
1620 .vol_control_A3 = 0x00000000, /* Vol Control A3 */ in hw_dac_init()
1621 .vol_control_B3 = 0x00000000, /* Vol Control B3 */ in hw_dac_init()
1622 .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */ in hw_dac_init()
1623 .vol_control_A4 = 0x00000000, /* Vol Control A4 */ in hw_dac_init()
1624 .vol_control_B4 = 0x00000000 /* Vol Control B4 */ in hw_dac_init()
1627 if (hw->model == CTSB1270) { in hw_dac_init()
1630 data &= ~0x0600; in hw_dac_init()
1631 if (1 == info->msr) in hw_dac_init()
1632 data |= 0x0000; /* Single Speed Mode 0-50kHz */ in hw_dac_init()
1633 else if (2 == info->msr) in hw_dac_init()
1634 data |= 0x0200; /* Double Speed Mode 50-100kHz */ in hw_dac_init()
1636 data |= 0x0600; /* Quad Speed Mode 100-200kHz */ in hw_dac_init()
1639 return 0; in hw_dac_init()
1644 data |= 0x02; in hw_dac_init()
1647 err = hw20k2_i2c_init(hw, 0x18, 1, 1); in hw_dac_init()
1648 if (err < 0) in hw_dac_init()
1651 for (i = 0; i < 2; i++) { in hw_dac_init()
1652 /* Reset DAC twice just in-case the chip in hw_dac_init()
1719 hw20k2_i2c_write(hw, CS4382_MC1, 0x80); in hw_dac_init()
1720 hw20k2_i2c_write(hw, CS4382_MC2, 0x10); in hw_dac_init()
1721 if (1 == info->msr) { in hw_dac_init()
1722 hw20k2_i2c_write(hw, CS4382_XC1, 0x24); in hw_dac_init()
1723 hw20k2_i2c_write(hw, CS4382_XC2, 0x24); in hw_dac_init()
1724 hw20k2_i2c_write(hw, CS4382_XC3, 0x24); in hw_dac_init()
1725 hw20k2_i2c_write(hw, CS4382_XC4, 0x24); in hw_dac_init()
1726 } else if (2 == info->msr) { in hw_dac_init()
1727 hw20k2_i2c_write(hw, CS4382_XC1, 0x25); in hw_dac_init()
1728 hw20k2_i2c_write(hw, CS4382_XC2, 0x25); in hw_dac_init()
1729 hw20k2_i2c_write(hw, CS4382_XC3, 0x25); in hw_dac_init()
1730 hw20k2_i2c_write(hw, CS4382_XC4, 0x25); in hw_dac_init()
1732 hw20k2_i2c_write(hw, CS4382_XC1, 0x26); in hw_dac_init()
1733 hw20k2_i2c_write(hw, CS4382_XC2, 0x26); in hw_dac_init()
1734 hw20k2_i2c_write(hw, CS4382_XC3, 0x26); in hw_dac_init()
1735 hw20k2_i2c_write(hw, CS4382_XC4, 0x26); in hw_dac_init()
1738 return 0; in hw_dac_init()
1742 return -1; in hw_dac_init()
1746 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1747 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1749 #define WM8775_IC 0x0B
1750 #define WM8775_MMC 0x0C
1751 #define WM8775_AADCL 0x0E
1752 #define WM8775_AADCR 0x0F
1753 #define WM8775_ADCMC 0x15
1754 #define WM8775_RESET 0x17
1759 if (hw->model == CTSB1270) { in hw_is_adc_input_selected()
1767 data = (data & (0x1 << 14)) ? 1 : 0; in hw_is_adc_input_selected()
1770 data = (data & (0x1 << 14)) ? 0 : 1; in hw_is_adc_input_selected()
1773 data = 0; in hw_is_adc_input_selected()
1778 #define MIC_BOOST_0DB 0xCF
1788 adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */ in hw_wm8775_input_select()
1793 if (gain_in_db < -103) in hw_wm8775_input_select()
1794 gain_in_db = -103; in hw_wm8775_input_select()
1813 data |= (0x1 << 14); in hw_adc_input_select()
1815 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */ in hw_adc_input_select()
1818 data &= ~(0x1 << 14); in hw_adc_input_select()
1820 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */ in hw_adc_input_select()
1826 return 0; in hw_adc_input_select()
1836 data |= (0x1 << 15); in hw_adc_init()
1840 err = hw20k2_i2c_init(hw, 0x1A, 1, 1); in hw_adc_init()
1841 if (err < 0) { in hw_adc_init()
1842 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n"); in hw_adc_init()
1848 data &= ~(0x1 << 15); in hw_adc_init()
1851 if (hw->model == CTSB1270) { in hw_adc_init()
1853 data &= ~0x0C; in hw_adc_init()
1854 if (1 == info->msr) in hw_adc_init()
1855 data |= 0x00; /* Single Speed Mode 32-50kHz */ in hw_adc_init()
1856 else if (2 == info->msr) in hw_adc_init()
1857 data |= 0x08; /* Double Speed Mode 50-108kHz */ in hw_adc_init()
1859 data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */ in hw_adc_init()
1865 data |= (0x1 << 15); in hw_adc_init()
1869 /* I2C write to register offset 0x0B to set ADC LRCLK polarity */ in hw_adc_init()
1870 /* invert bit, interface format to I2S, word length to 24-bit, */ in hw_adc_init()
1872 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26), in hw_adc_init()
1873 MAKE_WM8775_DATA(0x26)); in hw_adc_init()
1876 if (1 == info->msr) { in hw_adc_init()
1878 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02), in hw_adc_init()
1879 MAKE_WM8775_DATA(0x02)); in hw_adc_init()
1880 } else if ((2 == info->msr) || (4 == info->msr)) { in hw_adc_init()
1882 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A), in hw_adc_init()
1883 MAKE_WM8775_DATA(0x0A)); in hw_adc_init()
1885 dev_alert(hw->card->dev, in hw_adc_init()
1887 info->msr); in hw_adc_init()
1888 err = -EINVAL; in hw_adc_init()
1892 if (hw->model != CTSB1270) { in hw_adc_init()
1893 /* Configure GPIO bit 14 change to line-in/mic-in */ in hw_adc_init()
1895 ctl |= 0x1 << 14; in hw_adc_init()
1899 hw_wm8775_input_select(hw, 0, 0); in hw_adc_init()
1902 return 0; in hw_adc_init()
1912 cap.digit_io_switch = 0; in hw_capabilities()
1913 cap.dedicated_mic = hw->model == CTSB1270; in hw_capabilities()
1914 cap.output_switch = hw->model == CTSB1270; in hw_capabilities()
1915 cap.mic_source_switch = hw->model == CTSB1270; in hw_capabilities()
1924 switch (data & 0x30) { in hw_output_switch_get()
1925 case 0x00: in hw_output_switch_get()
1926 return 0; in hw_output_switch_get()
1927 case 0x10: in hw_output_switch_get()
1929 case 0x20: in hw_output_switch_get()
1941 return 0; in hw_output_switch_put()
1943 /* Mute line and headphones (intended for anti-pop). */ in hw_output_switch_put()
1945 data |= (0x03 << 11); in hw_output_switch_put()
1948 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30; in hw_output_switch_put()
1950 case 0: in hw_output_switch_put()
1953 data |= 0x10; in hw_output_switch_put()
1956 data |= 0x20; in hw_output_switch_put()
1962 data &= ~(0x03 << 11); in hw_output_switch_put()
1972 return hw20k2->mic_source; in hw_mic_source_switch_get()
1979 if (position == hw20k2->mic_source) in hw_mic_source_switch_put()
1980 return 0; in hw_mic_source_switch_put()
1983 case 0: in hw_mic_source_switch_put()
1984 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */ in hw_mic_source_switch_put()
1987 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */ in hw_mic_source_switch_put()
1990 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */ in hw_mic_source_switch_put()
1993 return 0; in hw_mic_source_switch_put()
1996 hw20k2->mic_source = position; in hw_mic_source_switch_put()
2010 if (hw->irq_callback) in ct_20k2_interrupt()
2011 hw->irq_callback(hw->irq_callback_data, status); in ct_20k2_interrupt()
2019 int err = 0; in hw_card_start()
2020 struct pci_dev *pci = hw->pci; in hw_card_start()
2025 if (err < 0) in hw_card_start()
2029 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) in hw_card_start()
2030 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); in hw_card_start()
2032 if (!hw->io_base) { in hw_card_start()
2034 if (err < 0) in hw_card_start()
2037 hw->io_base = pci_resource_start(hw->pci, 2); in hw_card_start()
2038 hw->mem_base = ioremap(hw->io_base, in hw_card_start()
2039 pci_resource_len(hw->pci, 2)); in hw_card_start()
2040 if (!hw->mem_base) { in hw_card_start()
2041 err = -ENOENT; in hw_card_start()
2048 set_field(&gctl, GCTL_UAA, 0); in hw_card_start()
2051 if (hw->irq < 0) { in hw_card_start()
2052 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED, in hw_card_start()
2054 if (err < 0) { in hw_card_start()
2055 dev_err(hw->card->dev, in hw_card_start()
2056 "XFi: Cannot get irq %d\n", pci->irq); in hw_card_start()
2059 hw->irq = pci->irq; in hw_card_start()
2060 hw->card->sync_irq = hw->irq; in hw_card_start()
2065 return 0; in hw_card_start()
2068 iounmap((void *)hw->mem_base); in hw_card_start()
2069 hw->mem_base = (unsigned long)NULL;*/ in hw_card_start()
2072 hw->io_base = 0; in hw_card_start()
2083 hw_write_20kx(hw, TRANSPORT_CTL, 0x00); in hw_card_stop()
2087 hw_write_20kx(hw, PLL_ENB, (data & (~0x07))); in hw_card_stop()
2090 return 0; in hw_card_stop()
2095 if (hw->irq >= 0) in hw_card_shutdown()
2096 free_irq(hw->irq, hw); in hw_card_shutdown()
2098 hw->irq = -1; in hw_card_shutdown()
2099 iounmap(hw->mem_base); in hw_card_shutdown()
2100 hw->mem_base = NULL; in hw_card_shutdown()
2102 if (hw->io_base) in hw_card_shutdown()
2103 pci_release_regions(hw->pci); in hw_card_shutdown()
2105 hw->io_base = 0; in hw_card_shutdown()
2107 pci_disable_device(hw->pci); in hw_card_shutdown()
2109 return 0; in hw_card_shutdown()
2116 u32 data = 0; in hw_card_init()
2117 struct dac_conf dac_info = {0}; in hw_card_init()
2118 struct adc_conf adc_info = {0}; in hw_card_init()
2119 struct daio_conf daio_info = {0}; in hw_card_init()
2120 struct trn_conf trn_info = {0}; in hw_card_init()
2129 err = hw_pll_init(hw, info->rsr); in hw_card_init()
2130 if (err < 0) in hw_card_init()
2133 /* kick off auto-init */ in hw_card_init()
2135 if (err < 0) in hw_card_init()
2142 set_field(&gctl, GCTL_DPC, 0); in hw_card_init()
2146 hw_write_20kx(hw, GIE, 0); in hw_card_init()
2148 hw_write_20kx(hw, SRC_IP, 0); in hw_card_init()
2150 if (hw->model != CTSB1270) { in hw_card_init()
2152 /* Configures GPIO (0xD802 0x98028) */ in hw_card_init()
2153 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/ in hw_card_init()
2155 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/ in hw_card_init()
2156 hw_write_20kx(hw, GPIO_CTRL, 0xD802); in hw_card_init()
2158 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F); in hw_card_init()
2161 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01); in hw_card_init()
2163 trn_info.vm_pgt_phys = info->vm_pgt_phys; in hw_card_init()
2165 if (err < 0) in hw_card_init()
2168 daio_info.msr = info->msr; in hw_card_init()
2170 if (err < 0) in hw_card_init()
2173 dac_info.msr = info->msr; in hw_card_init()
2175 if (err < 0) in hw_card_init()
2178 adc_info.msr = info->msr; in hw_card_init()
2180 adc_info.mic20db = 0; in hw_card_init()
2182 if (err < 0) in hw_card_init()
2186 data |= 0x1; /* Enables input from the audio ring */ in hw_card_init()
2189 return 0; in hw_card_init()
2196 return 0; in hw_suspend()
2201 /* Re-initialize card hardware. */ in hw_resume()
2208 return readl(hw->mem_base + reg); in hw_read_20kx()
2213 writel(data, hw->mem_base + reg); in hw_write_20kx()
2217 .irq = -1,
2331 return -ENOMEM; in create_20k2_hw_obj()
2333 hw20k2->hw = ct20k2_preset; in create_20k2_hw_obj()
2334 *rhw = &hw20k2->hw; in create_20k2_hw_obj()
2336 return 0; in create_20k2_hw_obj()
2341 if (hw->io_base) in destroy_20k2_hw_obj()
2345 return 0; in destroy_20k2_hw_obj()