Lines Matching +full:0 +full:x00000060
10 // Status register for MOTU 828 (0x'ffff'f000'0b00).
12 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
13 // 0x00008000: mode of optical input interface.
14 // 0x00008000: for S/PDIF signal.
15 // 0x00000000: disabled or for ADAT signal.
16 // 0x00004000: mode of optical output interface.
17 // 0x00004000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00003f00: monitor input mode.
20 // 0x00000800: analog-1/2
21 // 0x00001a00: analog-3/4
22 // 0x00002c00: analog-5/6
23 // 0x00003e00: analog-7/8
24 // 0x00000000: analog-1
25 // 0x00000900: analog-2
26 // 0x00001200: analog-3
27 // 0x00001b00: analog-4
28 // 0x00002400: analog-5
29 // 0x00002d00: analog-6
30 // 0x00003600: analog-7
31 // 0x00003f00: analog-8
32 // 0x00000080: enable stream input.
33 // 0x00000040: disable monitor input.
34 // 0x00000008: enable main out.
35 // 0x00000004: rate of sampling clock.
36 // 0x00000004: 48.0 kHz
37 // 0x00000000: 44.1 kHz
38 // 0x00000023: source of sampling clock.
39 // 0x00000003: source packet header (SPH)
40 // 0x00000002: S/PDIF on optical/coaxial interface.
41 // 0x00000021: ADAT on optical interface
42 // 0x00000001: ADAT on Dsub 9pin
43 // 0x00000000: internal
45 #define CLK_828_STATUS_OFFSET 0x0b00
46 #define CLK_828_STATUS_MASK 0x0000ffff
47 #define CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF 0x00008000
48 #define CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF 0x00004000
49 #define CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES 0x00000080
50 #define CLK_828_STATUS_FLAG_ENABLE_OUTPUT 0x00000008
51 #define CLK_828_STATUS_FLAG_RATE_48000 0x00000004
52 #define CLK_828_STATUS_MASK_SRC 0x00000023
53 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000021
54 #define CLK_828_STATUS_FLAG_SRC_SPH 0x00000003
55 #define CLK_828_STATUS_FLAG_SRC_SPDIF 0x00000002
56 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000001
57 #define CLK_828_STATUS_FLAG_SRC_INTERNAL 0x00000000
59 // Status register for MOTU 896 (0x'ffff'f000'0b14).
61 // 0xf0000000: enable physical and stream input to DAC.
62 // 0x80000000: disable
63 // 0x40000000: disable
64 // 0x20000000: enable (prior to the other bits)
65 // 0x10000000: disable
66 // 0x00000000: disable
67 // 0x08000000: speed of word clock signal output on BNC interface.
68 // 0x00000000: force to low rate (44.1/48.0 kHz).
69 // 0x08000000: follow to system clock.
70 // 0x04000000: something relevant to clock.
71 // 0x03000000: enable output.
72 // 0x02000000: enabled irreversibly once standing unless the device voluntarily disables it.
73 // 0x01000000: enabled irreversibly once standing unless the device voluntarily disables it.
74 // 0x00ffff00: monitor input mode.
75 // 0x00000000: disabled
76 // 0x00004800: analog-1/2
77 // 0x00005a00: analog-3/4
78 // 0x00006c00: analog-5/6
79 // 0x00007e00: analog-7/8
80 // 0x00104800: AES/EBU-1/2
81 // 0x00004000: analog-1
82 // 0x00004900: analog-2
83 // 0x00005200: analog-3
84 // 0x00005b00: analog-4
85 // 0x00006400: analog-5
86 // 0x00006d00: analog-6
87 // 0x00007600: analog-7
88 // 0x00007f00: analog-8
89 // 0x00104000: AES/EBU-1
90 // 0x00104900: AES/EBU-2
91 // 0x00000060: sample rate conversion for AES/EBU input/output.
92 // 0x00000000: None
93 // 0x00000020: input signal is converted to system rate
94 // 0x00000040: output is slave to input, ignoring system rate
95 // 0x00000060: output is double rate than system rate
96 // 0x00000018: nominal rate of sampling clock.
97 // 0x00000000: 44.1 kHz
98 // 0x00000008: 48.0 kHz
99 // 0x00000010: 88.2 kHz
100 // 0x00000018: 96.0 kHz
101 // 0x00000007: source of sampling clock.
102 // 0x00000000: internal
103 // 0x00000001: ADAT on optical interface
104 // 0x00000002: AES/EBU on XLR
105 // 0x00000003: source packet header (SPH)
106 // 0x00000004: word clock on BNC
107 // 0x00000005: ADAT on Dsub 9pin
109 #define CLK_896_STATUS_OFFSET 0x0b14
110 #define CLK_896_STATUS_FLAG_FETCH_ENABLE 0x20000000
111 #define CLK_896_STATUS_FLAG_OUTPUT_ON 0x03000000
112 #define CLK_896_STATUS_MASK_SRC 0x00000007
113 #define CLK_896_STATUS_FLAG_SRC_INTERNAL 0x00000000
114 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000001
115 #define CLK_896_STATUS_FLAG_SRC_AESEBU 0x00000002
116 #define CLK_896_STATUS_FLAG_SRC_SPH 0x00000003
117 #define CLK_896_STATUS_FLAG_SRC_WORD 0x00000004
118 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000005
119 #define CLK_896_STATUS_MASK_RATE 0x00000018
120 #define CLK_896_STATUS_FLAG_RATE_44100 0x00000000
121 #define CLK_896_STATUS_FLAG_RATE_48000 0x00000008
122 #define CLK_896_STATUS_FLAG_RATE_88200 0x00000010
123 #define CLK_896_STATUS_FLAG_RATE_96000 0x00000018
139 if (err < 0) in get_clock_rate_828()
143 return 0; in get_clock_rate_828()
165 return 0; in parse_clock_rate_896()
174 if (err < 0) in get_clock_rate_896()
196 if (err < 0) in set_clock_rate_828()
216 if (err < 0) in set_clock_rate_896()
261 if (err < 0) in get_clock_source_828()
290 return 0; in get_clock_source_828()
300 if (err < 0) in get_clock_source_896()
327 return 0; in get_clock_source_896()
347 if (err < 0) in switch_fetching_mode_828()
371 if (err < 0) in switch_fetching_mode_896()
403 motu->rx_packet_formats.msg_chunks = 0; in detect_packet_formats_828()
406 if (err < 0) in detect_packet_formats_828()
412 motu->tx_packet_formats.pcm_chunks[0] += 8; in detect_packet_formats_828()
415 motu->rx_packet_formats.pcm_chunks[0] += 8; in detect_packet_formats_828()
417 return 0; in detect_packet_formats_828()
427 motu->tx_packet_formats.msg_chunks = 0; in detect_packet_formats_896()
428 motu->rx_packet_formats.msg_chunks = 0; in detect_packet_formats_896()
432 motu->tx_packet_formats.pcm_chunks[0] += 8; in detect_packet_formats_896()
435 motu->rx_packet_formats.pcm_chunks[0] += 8; in detect_packet_formats_896()
438 return 0; in detect_packet_formats_896()
453 return 0; in snd_motu_protocol_v1_cache_packet_formats()
459 .tx_fixed_pcm_chunks = {10, 0, 0},
460 .rx_fixed_pcm_chunks = {10, 0, 0},
465 .tx_fixed_pcm_chunks = {10, 10, 0},
466 .rx_fixed_pcm_chunks = {10, 10, 0},