Lines Matching +full:single +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
3 * Library implementing the most common irq chip callback functions
22 * irq_gc_noop - NOOP function
31 * irq_gc_mask_disable_reg - Mask chip via disable register
34 * Chip has separate enable/disable registers instead of a single mask
41 u32 mask = d->mask; in irq_gc_mask_disable_reg()
44 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_reg()
45 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_reg()
51 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
54 * Chip has a single mask register. Values of this register are cached
55 * and protected by gc->lock
61 u32 mask = d->mask; in irq_gc_mask_set_bit()
64 *ct->mask_cache |= mask; in irq_gc_mask_set_bit()
65 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_set_bit()
71 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
74 * Chip has a single mask register. Values of this register are cached
75 * and protected by gc->lock
81 u32 mask = d->mask; in irq_gc_mask_clr_bit()
84 *ct->mask_cache &= ~mask; in irq_gc_mask_clr_bit()
85 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); in irq_gc_mask_clr_bit()
91 * irq_gc_unmask_enable_reg - Unmask chip via enable register
94 * Chip has separate enable/disable registers instead of a single mask
101 u32 mask = d->mask; in irq_gc_unmask_enable_reg()
104 irq_reg_writel(gc, mask, ct->regs.enable); in irq_gc_unmask_enable_reg()
105 *ct->mask_cache |= mask; in irq_gc_unmask_enable_reg()
111 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
118 u32 mask = d->mask; in irq_gc_ack_set_bit()
121 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_ack_set_bit()
127 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
134 u32 mask = ~d->mask; in irq_gc_ack_clr_bit()
137 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_ack_clr_bit()
142 * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
146 * with separate enable/disable registers instead of a single mask
157 u32 mask = d->mask; in irq_gc_mask_disable_and_ack_set()
160 irq_reg_writel(gc, mask, ct->regs.disable); in irq_gc_mask_disable_and_ack_set()
161 *ct->mask_cache &= ~mask; in irq_gc_mask_disable_and_ack_set()
162 irq_reg_writel(gc, mask, ct->regs.ack); in irq_gc_mask_disable_and_ack_set()
167 * irq_gc_eoi - EOI interrupt
174 u32 mask = d->mask; in irq_gc_eoi()
177 irq_reg_writel(gc, mask, ct->regs.eoi); in irq_gc_eoi()
182 * irq_gc_set_wake - Set/clr wake bit for an interrupt
193 u32 mask = d->mask; in irq_gc_set_wake()
195 if (!(mask & gc->wake_enabled)) in irq_gc_set_wake()
196 return -EINVAL; in irq_gc_set_wake()
200 gc->wake_active |= mask; in irq_gc_set_wake()
202 gc->wake_active &= ~mask; in irq_gc_set_wake()
222 struct irq_chip_type *ct = gc->chip_types; in irq_init_generic_chip()
225 raw_spin_lock_init(&gc->lock); in irq_init_generic_chip()
226 gc->num_ct = num_ct; in irq_init_generic_chip()
227 gc->irq_base = irq_base; in irq_init_generic_chip()
228 gc->reg_base = reg_base; in irq_init_generic_chip()
230 ct[i].chip.name = name; in irq_init_generic_chip()
231 gc->chip_types->handler = handler; in irq_init_generic_chip()
235 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
236 * @name: Name of the irq chip
238 * @irq_base: Interrupt base nr for this chip
240 * @handler: Default flow handler associated with this chip
242 * Returns an initialized irq_chip_generic structure. The chip defaults
263 struct irq_chip_type *ct = gc->chip_types; in irq_gc_init_mask_cache()
264 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; in irq_gc_init_mask_cache()
267 for (i = 0; i < gc->num_ct; i++) { in irq_gc_init_mask_cache()
279 * irq_domain_alloc_generic_chips - Allocate generic chips for an irq domain
281 * @info: Generic chip information
298 if (d->gc) in irq_domain_alloc_generic_chips()
299 return -EBUSY; in irq_domain_alloc_generic_chips()
301 numchips = DIV_ROUND_UP(d->revmap_size, info->irqs_per_chip); in irq_domain_alloc_generic_chips()
303 return -EINVAL; in irq_domain_alloc_generic_chips()
305 /* Allocate a pointer, generic chip and chiptypes for each chip */ in irq_domain_alloc_generic_chips()
306 gc_sz = struct_size(gc, chip_types, info->num_ct); in irq_domain_alloc_generic_chips()
312 return -ENOMEM; in irq_domain_alloc_generic_chips()
313 dgc->irqs_per_chip = info->irqs_per_chip; in irq_domain_alloc_generic_chips()
314 dgc->num_chips = numchips; in irq_domain_alloc_generic_chips()
315 dgc->irq_flags_to_set = info->irq_flags_to_set; in irq_domain_alloc_generic_chips()
316 dgc->irq_flags_to_clear = info->irq_flags_to_clear; in irq_domain_alloc_generic_chips()
317 dgc->gc_flags = info->gc_flags; in irq_domain_alloc_generic_chips()
318 dgc->exit = info->exit; in irq_domain_alloc_generic_chips()
319 d->gc = dgc; in irq_domain_alloc_generic_chips()
321 /* Calc pointer to the first generic chip */ in irq_domain_alloc_generic_chips()
324 /* Store the pointer to the generic chip */ in irq_domain_alloc_generic_chips()
325 dgc->gc[i] = gc = tmp; in irq_domain_alloc_generic_chips()
326 irq_init_generic_chip(gc, info->name, info->num_ct, in irq_domain_alloc_generic_chips()
327 i * dgc->irqs_per_chip, NULL, in irq_domain_alloc_generic_chips()
328 info->handler); in irq_domain_alloc_generic_chips()
330 gc->domain = d; in irq_domain_alloc_generic_chips()
331 if (dgc->gc_flags & IRQ_GC_BE_IO) { in irq_domain_alloc_generic_chips()
332 gc->reg_readl = &irq_readl_be; in irq_domain_alloc_generic_chips()
333 gc->reg_writel = &irq_writel_be; in irq_domain_alloc_generic_chips()
336 if (info->init) { in irq_domain_alloc_generic_chips()
337 ret = info->init(gc); in irq_domain_alloc_generic_chips()
343 list_add_tail(&gc->list, &gc_list); in irq_domain_alloc_generic_chips()
345 /* Calc pointer to the next generic chip */ in irq_domain_alloc_generic_chips()
351 while (i--) { in irq_domain_alloc_generic_chips()
352 if (dgc->exit) in irq_domain_alloc_generic_chips()
353 dgc->exit(dgc->gc[i]); in irq_domain_alloc_generic_chips()
354 irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0); in irq_domain_alloc_generic_chips()
356 d->gc = NULL; in irq_domain_alloc_generic_chips()
363 * irq_domain_remove_generic_chips - Remove generic chips from an irq domain
368 struct irq_domain_chip_generic *dgc = d->gc; in irq_domain_remove_generic_chips()
374 for (i = 0; i < dgc->num_chips; i++) { in irq_domain_remove_generic_chips()
375 if (dgc->exit) in irq_domain_remove_generic_chips()
376 dgc->exit(dgc->gc[i]); in irq_domain_remove_generic_chips()
377 irq_remove_generic_chip(dgc->gc[i], ~0U, 0, 0); in irq_domain_remove_generic_chips()
379 d->gc = NULL; in irq_domain_remove_generic_chips()
385 * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
387 * @irqs_per_chip: Number of interrupts each chip handles (max 32)
389 * @name: Name of the irq chip
393 * @gcflags: Generic chip specific setup flags
418 struct irq_domain_chip_generic *dgc = d->gc; in __irq_get_domain_generic_chip()
422 return ERR_PTR(-ENODEV); in __irq_get_domain_generic_chip()
423 idx = hw_irq / dgc->irqs_per_chip; in __irq_get_domain_generic_chip()
424 if (idx >= dgc->num_chips) in __irq_get_domain_generic_chip()
425 return ERR_PTR(-EINVAL); in __irq_get_domain_generic_chip()
426 return dgc->gc[idx]; in __irq_get_domain_generic_chip()
430 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
444 * Separate lockdep classes for interrupt chip which can nest irq_desc
451 * irq_map_generic_chip - Map a generic chip for an irq domain
457 struct irq_domain_chip_generic *dgc = d->gc; in irq_map_generic_chip()
460 struct irq_chip *chip; in irq_map_generic_chip() local
468 idx = hw_irq % dgc->irqs_per_chip; in irq_map_generic_chip()
470 if (test_bit(idx, &gc->unused)) in irq_map_generic_chip()
471 return -ENOTSUPP; in irq_map_generic_chip()
473 if (test_bit(idx, &gc->installed)) in irq_map_generic_chip()
474 return -EBUSY; in irq_map_generic_chip()
476 ct = gc->chip_types; in irq_map_generic_chip()
477 chip = &ct->chip; in irq_map_generic_chip()
479 /* We only init the cache for the first mapping of a generic chip */ in irq_map_generic_chip()
480 if (!gc->installed) { in irq_map_generic_chip()
481 raw_spin_lock_irqsave(&gc->lock, flags); in irq_map_generic_chip()
482 irq_gc_init_mask_cache(gc, dgc->gc_flags); in irq_map_generic_chip()
483 raw_spin_unlock_irqrestore(&gc->lock, flags); in irq_map_generic_chip()
487 set_bit(idx, &gc->installed); in irq_map_generic_chip()
489 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK) in irq_map_generic_chip()
493 if (chip->irq_calc_mask) in irq_map_generic_chip()
494 chip->irq_calc_mask(data); in irq_map_generic_chip()
496 data->mask = 1 << idx; in irq_map_generic_chip()
498 irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL); in irq_map_generic_chip()
499 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set); in irq_map_generic_chip()
506 struct irq_domain_chip_generic *dgc = d->gc; in irq_unmap_generic_chip()
507 unsigned int hw_irq = data->hwirq; in irq_unmap_generic_chip()
515 irq_idx = hw_irq % dgc->irqs_per_chip; in irq_unmap_generic_chip()
517 clear_bit(irq_idx, &gc->installed); in irq_unmap_generic_chip()
531 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
532 * @gc: Generic irq chip holding all data
533 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
538 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
546 struct irq_chip_type *ct = gc->chip_types; in irq_setup_generic_chip()
547 struct irq_chip *chip = &ct->chip; in irq_setup_generic_chip() local
551 list_add_tail(&gc->list, &gc_list); in irq_setup_generic_chip()
556 for (i = gc->irq_base; msk; msk >>= 1, i++) { in irq_setup_generic_chip()
567 if (chip->irq_calc_mask) in irq_setup_generic_chip()
568 chip->irq_calc_mask(d); in irq_setup_generic_chip()
570 d->mask = 1 << (i - gc->irq_base); in irq_setup_generic_chip()
572 irq_set_chip_and_handler(i, chip, ct->handler); in irq_setup_generic_chip()
576 gc->irq_cnt = i - gc->irq_base; in irq_setup_generic_chip()
581 * irq_setup_alt_chip - Switch to alternative chip
585 * Only to be called from chip->irq_set_type() callbacks.
590 struct irq_chip_type *ct = gc->chip_types; in irq_setup_alt_chip()
593 for (i = 0; i < gc->num_ct; i++, ct++) { in irq_setup_alt_chip()
594 if (ct->type & type) { in irq_setup_alt_chip()
595 d->chip = &ct->chip; in irq_setup_alt_chip()
596 irq_data_to_desc(d)->handle_irq = ct->handler; in irq_setup_alt_chip()
600 return -EINVAL; in irq_setup_alt_chip()
605 * irq_remove_generic_chip - Remove a chip
606 * @gc: Generic irq chip holding all data
607 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
611 * Remove up to 32 interrupts starting from gc->irq_base.
619 list_del(&gc->list); in irq_remove_generic_chip()
631 if (gc->domain) { in irq_remove_generic_chip()
632 virq = irq_find_mapping(gc->domain, gc->irq_base + i); in irq_remove_generic_chip()
636 virq = gc->irq_base + i; in irq_remove_generic_chip()
652 if (!gc->domain) in irq_gc_get_irq_data()
653 return irq_get_irq_data(gc->irq_base); in irq_gc_get_irq_data()
659 if (!gc->installed) in irq_gc_get_irq_data()
662 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed)); in irq_gc_get_irq_data()
672 struct irq_chip_type *ct = gc->chip_types; in irq_gc_suspend()
674 if (ct->chip.irq_suspend) { in irq_gc_suspend()
678 ct->chip.irq_suspend(data); in irq_gc_suspend()
681 if (gc->suspend) in irq_gc_suspend()
682 gc->suspend(gc); in irq_gc_suspend()
692 struct irq_chip_type *ct = gc->chip_types; in irq_gc_resume()
694 if (gc->resume) in irq_gc_resume()
695 gc->resume(gc); in irq_gc_resume()
697 if (ct->chip.irq_resume) { in irq_gc_resume()
701 ct->chip.irq_resume(data); in irq_gc_resume()
715 struct irq_chip_type *ct = gc->chip_types; in irq_gc_shutdown()
717 if (ct->chip.irq_pm_shutdown) { in irq_gc_shutdown()
721 ct->chip.irq_pm_shutdown(data); in irq_gc_shutdown()