Lines Matching +full:0 +full:x000003ff
29 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
30 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
31 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
32 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
33 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
34 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
35 #define iACC3 0x06 /* R = A + X + Y ; saturation */
36 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
37 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
38 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
39 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
40 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
41 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
42 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
43 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
44 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
46 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
47 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
48 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
49 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
50 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
53 #define A_LOWORD_OPX_MASK 0x007ff000
54 #define A_LOWORD_OPY_MASK 0x000007ff
55 #define A_HIWORD_OPCODE_MASK 0x0f000000
56 #define A_HIWORD_RESULT_MASK 0x007ff000
57 #define A_HIWORD_OPA_MASK 0x000007ff
60 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
61 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
62 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
63 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bi…
64 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
66 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
67 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
68 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
69 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
70 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
71 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" */
72 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_01 - _0F" */
73 #define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x1f "EMU32_IN_00 - _1F" - Only when .device = 0x…
74 #define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x1f "EMU32_OUT_00 - _1F" - Only when .device = …
76 #define C_00000000 0x40
77 #define C_00000001 0x41
78 #define C_00000002 0x42
79 #define C_00000003 0x43
80 #define C_00000004 0x44
81 #define C_00000008 0x45
82 #define C_00000010 0x46
83 #define C_00000020 0x47
84 #define C_00000100 0x48
85 #define C_00010000 0x49
86 #define C_00080000 0x4a
87 #define C_10000000 0x4b
88 #define C_20000000 0x4c
89 #define C_40000000 0x4d
90 #define C_80000000 0x4e
91 #define C_7fffffff 0x4f
92 #define C_ffffffff 0x50
93 #define C_fffffffe 0x51
94 #define C_c0000000 0x52
95 #define C_4f1bbcdc 0x53
96 #define C_5a7ef9db 0x54
97 #define C_00100000 0x55 /* ?? */
98 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
99 #define GPR_COND 0x57 /* CCR, condition register */
100 #define GPR_NOISE0 0x58 /* noise source */
101 #define GPR_NOISE1 0x59 /* noise source */
102 #define GPR_IRQ 0x5a /* IRQ register */
103 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
106 #define A_C_00000000 0xc0
107 #define A_C_00000001 0xc1
108 #define A_C_00000002 0xc2
109 #define A_C_00000003 0xc3
110 #define A_C_00000004 0xc4
111 #define A_C_00000008 0xc5
112 #define A_C_00000010 0xc6
113 #define A_C_00000020 0xc7
114 #define A_C_00000100 0xc8
115 #define A_C_00010000 0xc9
116 #define A_C_00000800 0xca
117 #define A_C_10000000 0xcb
118 #define A_C_20000000 0xcc
119 #define A_C_40000000 0xcd
120 #define A_C_80000000 0xce
121 #define A_C_7fffffff 0xcf
122 #define A_C_ffffffff 0xd0
123 #define A_C_fffffffe 0xd1
124 #define A_C_c0000000 0xd2
125 #define A_C_4f1bbcdc 0xd3
126 #define A_C_5a7ef9db 0xd4
127 #define A_C_00100000 0xd5
128 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
129 #define A_GPR_COND 0xd7 /* CCR, condition register */
130 #define A_GPR_NOISE0 0xd8 /* noise source */
131 #define A_GPR_NOISE1 0xd9 /* noise source */
132 #define A_GPR_IRQ 0xda /* IRQ register */
133 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
134 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
137 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
138 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
140 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
141 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
146 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
147 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
150 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
151 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
152 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
153 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
154 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
155 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
157 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
158 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
159 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
160 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
161 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
164 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
165 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
166 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
167 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
168 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
169 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
190 #define FXBUS_PCM_LEFT 0x00
191 #define FXBUS_PCM_RIGHT 0x01
192 #define FXBUS_PCM_LEFT_REAR 0x02
193 #define FXBUS_PCM_RIGHT_REAR 0x03
194 #define FXBUS_MIDI_LEFT 0x04
195 #define FXBUS_MIDI_RIGHT 0x05
196 #define FXBUS_PCM_CENTER 0x06
197 #define FXBUS_PCM_LFE 0x07
198 #define FXBUS_PCM_LEFT_FRONT 0x08
199 #define FXBUS_PCM_RIGHT_FRONT 0x09
200 #define FXBUS_MIDI_REVERB 0x0c
201 #define FXBUS_MIDI_CHORUS 0x0d
202 #define FXBUS_PCM_LEFT_SIDE 0x0e
203 #define FXBUS_PCM_RIGHT_SIDE 0x0f
204 #define FXBUS_PT_LEFT 0x14
205 #define FXBUS_PT_RIGHT 0x15
208 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
209 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
210 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
211 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
212 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
213 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
214 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
215 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
216 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
217 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
218 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
219 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
220 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
221 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
224 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
225 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
226 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
227 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
228 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
229 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
230 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
231 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
232 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
233 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
234 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
235 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
236 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
237 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
238 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
239 #define EXTOUT_ACENTER 0x11 /* Analog Center */
240 #define EXTOUT_ALFE 0x12 /* Analog LFE */
243 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
244 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
245 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
246 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
247 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
248 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
249 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
250 #define A_EXTIN_LINE2_R 0x09 /* right */
251 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
252 #define A_EXTIN_ADC_R 0x0b /* right */
253 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
254 #define A_EXTIN_AUX2_R 0x0d /* - right */
257 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
258 #define A_EXTOUT_FRONT_R 0x01 /* right */
259 #define A_EXTOUT_CENTER 0x02 /* digital front center */
260 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
261 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
262 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
263 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
264 #define A_EXTOUT_REAR_R 0x07 /* right */
265 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
266 #define A_EXTOUT_AFRONT_R 0x09 /* right */
267 #define A_EXTOUT_ACENTER 0x0a /* analog center */
268 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
269 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
270 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
271 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
272 #define A_EXTOUT_AREAR_R 0x0f /* right */
273 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
274 #define A_EXTOUT_AC97_R 0x11 /* right */
275 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
276 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
277 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
280 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
281 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
282 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
283 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
284 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
285 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
286 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
289 #define A_DBG_ZC 0x40000000 /* zero tram counter */
290 #define A_DBG_SATURATION_OCCURED 0x20000000
291 #define A_DBG_SATURATION_ADDR 0x0ffc0000
292 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
293 #define A_DBG_STEP 0x00010000
294 #define A_DBG_CONDITION_CODE 0x0000f800
295 #define A_DBG_STEP_ADDR 0x000003ff
306 #define EMU10K1_GPR_TRANSLATION_NONE 0
355 __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
368 __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
400 #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
402 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
403 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
404 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
405 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
406 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
407 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
408 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
409 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
410 #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
411 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
412 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
413 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
414 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
415 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)