Lines Matching refs:V4L2_DV_VSYNC_POS_POL
78 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
87 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
96 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
106 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
115 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
125 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
135 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
144 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
154 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
164 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
173 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
184 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
194 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
205 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
215 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
226 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
235 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
245 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
256 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
265 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
275 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
284 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
303 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
310 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
343 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
351 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
359 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
367 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
375 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
391 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
399 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
422 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
430 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
447 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
472 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
479 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
509 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
516 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
532 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
540 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
557 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
565 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
573 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
589 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
605 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
613 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
629 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
636 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
643 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
667 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
674 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
681 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
697 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
706 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
714 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
722 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
730 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
738 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
762 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
769 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
776 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
791 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
798 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
813 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
820 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
846 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
853 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
860 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
875 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
882 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
898 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
914 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
921 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
928 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \