Lines Matching full:1280
77 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
105 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
114 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
457 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
465 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
472 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
479 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
486 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
494 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
502 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
509 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
516 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
523 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
531 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
539 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
547 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
556 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
564 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
572 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
580 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \