Lines Matching +full:delta +full:- +full:x +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
101 #define UART_FCR_R_TRIG_BITS(x) \ argument
102 (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
132 #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
142 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
155 #define UART_MSR_DDCD 0x08 /* Delta DCD */
157 #define UART_MSR_DDSR 0x02 /* Delta DSR */
158 #define UART_MSR_DCTS 0x01 /* Delta CTS */
239 * The Intel XScale on-chip UARTs define these bits
248 #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
249 #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
250 #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
251 #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
275 #define UART_NMR 0x0D /* Nine-bit Mode Register */
291 * These definitions are for the RSA-DV II/S card, from
293 * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
296 #define UART_RSA_BASE (-8)
343 #define UART_DA830_PWREMU_MGMT_FREE (1 << 0) /* Free-running mode */
363 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
369 #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
371 #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
372 #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */