Lines Matching +full:8 +full:xx
62 * PC16550D: 1 4 8 14 xx xx xx xx
63 * TI16C550A: 1 4 8 14 xx xx xx xx
64 * TI16C550C: 1 4 8 14 xx xx xx xx
65 * ST16C550: 1 4 8 14 xx xx xx xx
66 * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
67 * NS16C552: 1 4 8 14 xx xx xx xx
68 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
69 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
70 * TI16C752: 8 16 56 60 8 16 32 56
72 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
86 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
91 #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
94 #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
119 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
249 #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
296 #define UART_RSA_BASE (-8)
300 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
334 * standard rate, and the other is 8 times faster.
337 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)