Lines Matching +full:0 +full:x70000000
26 #define PT_NULL 0
34 #define PT_LOOS 0x60000000 /* OS-specific */
35 #define PT_HIOS 0x6fffffff /* OS-specific */
36 #define PT_LOPROC 0x70000000
37 #define PT_HIPROC 0x7fffffff
38 #define PT_GNU_EH_FRAME (PT_LOOS + 0x474e550)
39 #define PT_GNU_STACK (PT_LOOS + 0x474e551)
40 #define PT_GNU_RELRO (PT_LOOS + 0x474e552)
41 #define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
45 #define PT_AARCH64_MEMTAG_MTE (PT_LOPROC + 0x2)
51 * or equal to PN_XNUM(0xffff), it is set to sh_info field of the
52 * section header at index 0, and PN_XNUM is set to e_phnum
53 * field. Otherwise, the section header at index 0 is zero
67 #define PN_XNUM 0xffff
70 #define ET_NONE 0
75 #define ET_LOPROC 0xff00
76 #define ET_HIPROC 0xffff
79 #define DT_NULL 0
104 #define OLD_DT_LOOS 0x60000000
105 #define DT_LOOS 0x6000000d
106 #define DT_HIOS 0x6ffff000
107 #define DT_VALRNGLO 0x6ffffd00
108 #define DT_VALRNGHI 0x6ffffdff
109 #define DT_ADDRRNGLO 0x6ffffe00
110 #define DT_ADDRRNGHI 0x6ffffeff
111 #define DT_VERSYM 0x6ffffff0
112 #define DT_RELACOUNT 0x6ffffff9
113 #define DT_RELCOUNT 0x6ffffffa
114 #define DT_FLAGS_1 0x6ffffffb
115 #define DT_VERDEF 0x6ffffffc
116 #define DT_VERDEFNUM 0x6ffffffd
117 #define DT_VERNEED 0x6ffffffe
118 #define DT_VERNEEDNUM 0x6fffffff
119 #define OLD_DT_HIOS 0x6fffffff
120 #define DT_LOPROC 0x70000000
121 #define DT_HIPROC 0x7fffffff
124 #define STB_LOCAL 0
128 #define STT_NOTYPE 0
137 #define ELF_ST_TYPE(x) ((x) & 0xf)
161 #define ELF32_R_TYPE(x) ((x) & 0xff)
164 #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
200 unsigned char st_other; /* No defined meaning, 0 */
245 #define PF_R 0x4
246 #define PF_W 0x2
247 #define PF_X 0x1
272 #define SHT_NULL 0
285 #define SHT_LOPROC 0x70000000
286 #define SHT_HIPROC 0x7fffffff
287 #define SHT_LOUSER 0x80000000
288 #define SHT_HIUSER 0xffffffff
291 #define SHF_WRITE 0x1
292 #define SHF_ALLOC 0x2
293 #define SHF_EXECINSTR 0x4
294 #define SHF_RELA_LIVEPATCH 0x00100000
295 #define SHF_RO_AFTER_INIT 0x00200000
296 #define SHF_MASKPROC 0xf0000000
299 #define SHN_UNDEF 0
300 #define SHN_LORESERVE 0xff00
301 #define SHN_LOPROC 0xff00
302 #define SHN_HIPROC 0xff1f
303 #define SHN_LIVEPATCH 0xff20
304 #define SHN_ABS 0xfff1
305 #define SHN_COMMON 0xfff2
306 #define SHN_HIRESERVE 0xffff
334 #define EI_MAG0 0 /* e_ident[] indexes */
344 #define ELFMAG0 0x7f /* EI_MAG */
351 #define ELFCLASSNONE 0 /* EI_CLASS */
356 #define ELFDATANONE 0 /* e_ident[EI_DATA] */
360 #define EV_NONE 0 /* e_version, EI_VERSION */
364 #define ELFOSABI_NONE 0
387 #define NT_SIGINFO 0x53494749
388 #define NT_FILE 0x46494c45
389 #define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */
390 #define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */
391 #define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */
392 #define NT_PPC_VSX 0x102 /* PowerPC VSX registers */
393 #define NT_PPC_TAR 0x103 /* Target Address Register */
394 #define NT_PPC_PPR 0x104 /* Program Priority Register */
395 #define NT_PPC_DSCR 0x105 /* Data Stream Control Register */
396 #define NT_PPC_EBB 0x106 /* Event Based Branch Registers */
397 #define NT_PPC_PMU 0x107 /* Performance Monitor Registers */
398 #define NT_PPC_TM_CGPR 0x108 /* TM checkpointed GPR Registers */
399 #define NT_PPC_TM_CFPR 0x109 /* TM checkpointed FPR Registers */
400 #define NT_PPC_TM_CVMX 0x10a /* TM checkpointed VMX Registers */
401 #define NT_PPC_TM_CVSX 0x10b /* TM checkpointed VSX Registers */
402 #define NT_PPC_TM_SPR 0x10c /* TM Special Purpose Registers */
403 #define NT_PPC_TM_CTAR 0x10d /* TM checkpointed Target Address Register */
404 #define NT_PPC_TM_CPPR 0x10e /* TM checkpointed Program Priority Register */
405 #define NT_PPC_TM_CDSCR 0x10f /* TM checkpointed Data Stream Control Register */
406 #define NT_PPC_PKEY 0x110 /* Memory Protection Keys registers */
407 #define NT_PPC_DEXCR 0x111 /* PowerPC DEXCR registers */
408 #define NT_PPC_HASHKEYR 0x112 /* PowerPC HASHKEYR register */
409 #define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */
410 #define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */
411 #define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */
412 /* Old binutils treats 0x203 as a CET state */
413 #define NT_X86_SHSTK 0x204 /* x86 SHSTK state */
414 #define NT_X86_XSAVE_LAYOUT 0x205 /* XSAVE layout description */
415 #define NT_S390_HIGH_GPRS 0x300 /* s390 upper register halves */
416 #define NT_S390_TIMER 0x301 /* s390 timer register */
417 #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */
418 #define NT_S390_TODPREG 0x303 /* s390 TOD programmable register */
419 #define NT_S390_CTRS 0x304 /* s390 control registers */
420 #define NT_S390_PREFIX 0x305 /* s390 prefix register */
421 #define NT_S390_LAST_BREAK 0x306 /* s390 breaking event address */
422 #define NT_S390_SYSTEM_CALL 0x307 /* s390 system call restart data */
423 #define NT_S390_TDB 0x308 /* s390 transaction diagnostic block */
424 #define NT_S390_VXRS_LOW 0x309 /* s390 vector registers 0-15 upper half */
425 #define NT_S390_VXRS_HIGH 0x30a /* s390 vector registers 16-31 */
426 #define NT_S390_GS_CB 0x30b /* s390 guarded storage registers */
427 #define NT_S390_GS_BC 0x30c /* s390 guarded storage broadcast control block */
428 #define NT_S390_RI_CB 0x30d /* s390 runtime instrumentation */
429 #define NT_S390_PV_CPU_DATA 0x30e /* s390 protvirt cpu dump data */
430 #define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */
431 #define NT_ARM_TLS 0x401 /* ARM TLS register */
432 #define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */
433 #define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */
434 #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */
435 #define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension registers */
436 #define NT_ARM_PAC_MASK 0x406 /* ARM pointer authentication code masks */
437 #define NT_ARM_PACA_KEYS 0x407 /* ARM pointer authentication address keys */
438 #define NT_ARM_PACG_KEYS 0x408 /* ARM pointer authentication generic key */
439 #define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* arm64 tagged address control (prctl()) */
440 #define NT_ARM_PAC_ENABLED_KEYS 0x40a /* arm64 ptr auth enabled keys (prctl()) */
441 #define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers */
442 #define NT_ARM_ZA 0x40c /* ARM SME ZA registers */
443 #define NT_ARM_ZT 0x40d /* ARM SME ZT registers */
444 #define NT_ARM_FPMR 0x40e /* ARM floating point mode register */
445 #define NT_ARM_POE 0x40f /* ARM POE registers */
446 #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */
447 #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */
448 #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
449 #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
450 #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
451 #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
452 #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
453 #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
454 #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
455 #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
456 #define NT_LOONGARCH_LASX 0xa03 /* LoongArch Loongson Advanced SIMD Extension registers */
457 #define NT_LOONGARCH_LBT 0xa04 /* LoongArch Loongson Binary Translation registers */
458 #define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint registers */
459 #define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint registers */
479 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
482 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)