uapi/drm/radeon_drm.h

51 #define RADEON_UPLOAD_CONTEXT		0x00000001
52 #define RADEON_UPLOAD_VERTFMT		0x00000002
53 #define RADEON_UPLOAD_LINE		0x00000004
54 #define RADEON_UPLOAD_BUMPMAP		0x00000008
55 #define RADEON_UPLOAD_MASKS		0x00000010
56 #define RADEON_UPLOAD_VIEWPORT		0x00000020
57 #define RADEON_UPLOAD_SETUP		0x00000040
58 #define RADEON_UPLOAD_TCL		0x00000080
59 #define RADEON_UPLOAD_MISC		0x00000100
60 #define RADEON_UPLOAD_TEX0		0x00000200
61 #define RADEON_UPLOAD_TEX1		0x00000400
62 #define RADEON_UPLOAD_TEX2		0x00000800
63 #define RADEON_UPLOAD_TEX0IMAGES	0x00001000
64 #define RADEON_UPLOAD_TEX1IMAGES	0x00002000
65 #define RADEON_UPLOAD_TEX2IMAGES	0x00004000
66 #define RADEON_UPLOAD_CLIPRECTS		0x00008000	/* handled client-side */
67 #define RADEON_REQUIRE_QUIESCENCE	0x00010000
68 #define RADEON_UPLOAD_ZBIAS		0x00020000	/* version 1.2 and newer */
69 #define RADEON_UPLOAD_ALL		0x003effff
70 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
76 #define RADEON_EMIT_PP_MISC                         0	/* context/7 */
213 #define RADEON_WAIT_2D  0x1
214 #define RADEON_WAIT_3D  0x2
218 #define R300_CMD_PACKET3_CLEAR		0
232 #	define R300_WAIT_2D		0x1
233 #	define R300_WAIT_3D		0x2
240 #	define R300_WAIT_2D_CLEAN	0x3
241 #	define R300_WAIT_3D_CLEAN	0x4
243 #	define R300_NEW_WAIT_2D_3D	0x3
244 #	define R300_NEW_WAIT_2D_2D_CLEAN	0x4
245 #	define R300_NEW_WAIT_3D_3D_CLEAN	0x6
246 #	define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN	0x8
283 #define RADEON_FRONT			0x1
284 #define RADEON_BACK			0x2
285 #define RADEON_DEPTH			0x4
286 #define RADEON_STENCIL			0x8
287 #define RADEON_CLEAR_FASTZ		0x80000000
288 #define RADEON_USE_HIERZ		0x40000000
289 #define RADEON_USE_COMP_ZBUF		0x20000000
296 #define RADEON_POINTS			0x1
297 #define RADEON_LINES			0x2
298 #define RADEON_LINE_STRIP		0x3
299 #define RADEON_TRIANGLES		0x4
300 #define RADEON_TRIANGLE_FAN		0x5
301 #define RADEON_TRIANGLE_STRIP		0x6
320 #define RADEON_LOCAL_TEX_HEAP		0
349 	unsigned int pp_misc;	/* 0x1c14 */
357 	unsigned int pp_cntl;	/* 0x1c38 */
365 	unsigned int se_coord_fmt;	/* 0x1c50 */
368 	unsigned int re_line_pattern;	/* 0x1cd0 */
371 	unsigned int se_line_width;	/* 0x1db8 */
374 	unsigned int pp_lum_matrix;	/* 0x1d00 */
376 	unsigned int pp_rot_matrix_0;	/* 0x1d58 */
380 	unsigned int rb3d_stencilrefmask;	/* 0x1d7c */
385 	unsigned int se_vport_xscale;	/* 0x1d98 */
393 	unsigned int se_cntl_status;	/* 0x2140 */
396 	unsigned int re_top_left;	/* 0x26c0 */
402 	unsigned int se_zbias_factor;	/* 0x1dac */
460 	int pfState;		/* number of 3d windows (0,1,2ormore) */
473  * The device specific ioctl range is 0x40 to 0x79.
475 #define DRM_RADEON_CP_INIT    0x00
476 #define DRM_RADEON_CP_START   0x01
477 #define DRM_RADEON_CP_STOP    0x02
478 #define DRM_RADEON_CP_RESET   0x03
479 #define DRM_RADEON_CP_IDLE    0x04
480 #define DRM_RADEON_RESET      0x05
481 #define DRM_RADEON_FULLSCREEN 0x06
482 #define DRM_RADEON_SWAP       0x07
483 #define DRM_RADEON_CLEAR      0x08
484 #define DRM_RADEON_VERTEX     0x09
485 #define DRM_RADEON_INDICES    0x0A
487 #define DRM_RADEON_STIPPLE    0x0C
488 #define DRM_RADEON_INDIRECT   0x0D
489 #define DRM_RADEON_TEXTURE    0x0E
490 #define DRM_RADEON_VERTEX2    0x0F
491 #define DRM_RADEON_CMDBUF     0x10
492 #define DRM_RADEON_GETPARAM   0x11
493 #define DRM_RADEON_FLIP       0x12
494 #define DRM_RADEON_ALLOC      0x13
495 #define DRM_RADEON_FREE       0x14
496 #define DRM_RADEON_INIT_HEAP  0x15
497 #define DRM_RADEON_IRQ_EMIT   0x16
498 #define DRM_RADEON_IRQ_WAIT   0x17
499 #define DRM_RADEON_CP_RESUME  0x18
500 #define DRM_RADEON_SETPARAM   0x19
501 #define DRM_RADEON_SURF_ALLOC 0x1a
502 #define DRM_RADEON_SURF_FREE  0x1b
504 #define DRM_RADEON_GEM_INFO		0x1c
505 #define DRM_RADEON_GEM_CREATE		0x1d
506 #define DRM_RADEON_GEM_MMAP		0x1e
507 #define DRM_RADEON_GEM_PREAD		0x21
508 #define DRM_RADEON_GEM_PWRITE		0x22
509 #define DRM_RADEON_GEM_SET_DOMAIN	0x23
510 #define DRM_RADEON_GEM_WAIT_IDLE	0x24
511 #define DRM_RADEON_CS			0x26
512 #define DRM_RADEON_INFO			0x27
513 #define DRM_RADEON_GEM_SET_TILING	0x28
514 #define DRM_RADEON_GEM_GET_TILING	0x29
515 #define DRM_RADEON_GEM_BUSY		0x2a
516 #define DRM_RADEON_GEM_VA		0x2b
517 #define DRM_RADEON_GEM_OP		0x2c
518 #define DRM_RADEON_GEM_USERPTR		0x2d
566 		RADEON_INIT_CP = 0x01,
567 		RADEON_CLEANUP_CP = 0x02,
568 		RADEON_INIT_R200_CP = 0x03,
569 		RADEON_INIT_R300_CP = 0x04,
570 		RADEON_INIT_R600_CP = 0x05
600 		RADEON_INIT_FULLSCREEN = 0x01,
601 		RADEON_CLEANUP_FULLSCREEN = 0x02
605 #define CLEAR_X1	0
697 #define RADEON_CARD_PCI 0
795 #define RADEON_GEM_DOMAIN_CPU		0x1
796 #define RADEON_GEM_DOMAIN_GTT		0x2
797 #define RADEON_GEM_DOMAIN_VRAM		0x4
805 #define RADEON_GEM_NO_BACKING_STORE	(1 << 0)
826 #define RADEON_GEM_USERPTR_READONLY	(1 << 0)
838 #define RADEON_TILING_MACRO				0x1
839 #define RADEON_TILING_MICRO				0x2
840 #define RADEON_TILING_SWAP_16BIT			0x4
841 #define RADEON_TILING_SWAP_32BIT			0x8
843 #define RADEON_TILING_SURFACE				0x10
844 #define RADEON_TILING_MICRO_SQUARE			0x20
846 #define RADEON_TILING_EG_BANKW_MASK			0xf
848 #define RADEON_TILING_EG_BANKH_MASK			0xf
850 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK		0xf
852 #define RADEON_TILING_EG_TILE_SPLIT_MASK		0xf
854 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK	0xf
925 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN	0
931 #define RADEON_VA_RESULT_OK		0
935 #define RADEON_VM_PAGE_VALID		(1 << 0)
949 #define RADEON_CHUNK_ID_RELOCS	0x01
950 #define RADEON_CHUNK_ID_IB	0x02
951 #define RADEON_CHUNK_ID_FLAGS	0x03
952 #define RADEON_CHUNK_ID_CONST_IB	0x04
955 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
956 #define RADEON_CS_USE_VM            0x02
957 #define RADEON_CS_END_OF_FRAME      0x04 /* a hint from userspace which CS is the last one */
959 #define RADEON_CS_RING_GFX          0
965 /* 0 = normal, + = higher priority, - = lower priority */
974 #define RADEON_RELOC_PRIO_MASK		(0xf << 0)
993 #define RADEON_INFO_DEVICE_ID		0x00
994 #define RADEON_INFO_NUM_GB_PIPES	0x01
995 #define RADEON_INFO_NUM_Z_PIPES 	0x02
996 #define RADEON_INFO_ACCEL_WORKING	0x03
997 #define RADEON_INFO_CRTC_FROM_ID	0x04
998 #define RADEON_INFO_ACCEL_WORKING2	0x05
999 #define RADEON_INFO_TILING_CONFIG	0x06
1000 #define RADEON_INFO_WANT_HYPERZ		0x07
1001 #define RADEON_INFO_WANT_CMASK		0x08 /* get access to CMASK on r300 */
1002 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ	0x09 /* clock crystal frequency */
1003 #define RADEON_INFO_NUM_BACKENDS	0x0a /* DB/backends for r600+ - need for OQ */
1004 #define RADEON_INFO_NUM_TILE_PIPES	0x0b /* tile pipes for r600+ */
1005 #define RADEON_INFO_FUSION_GART_WORKING	0x0c /* fusion writes to GTT were broken before this */
1006 #define RADEON_INFO_BACKEND_MAP		0x0d /* pipe to backend map, needed by mesa */
1008 #define RADEON_INFO_VA_START		0x0e
1010 #define RADEON_INFO_IB_VM_MAX_SIZE	0x0f
1012 #define RADEON_INFO_MAX_PIPES		0x10
1014 #define RADEON_INFO_TIMESTAMP		0x11
1016 #define RADEON_INFO_MAX_SE		0x12
1018 #define RADEON_INFO_MAX_SH_PER_SE	0x13
1020 #define RADEON_INFO_FASTFB_WORKING	0x14
1022 #define RADEON_INFO_RING_WORKING	0x15
1024 #define RADEON_INFO_SI_TILE_MODE_ARRAY	0x16
1026 #define RADEON_INFO_SI_CP_DMA_COMPUTE	0x17
1028 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY	0x18
1030 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK	0x19
1032 #define RADEON_INFO_MAX_SCLK		0x1a
1034 #define RADEON_INFO_VCE_FW_VERSION	0x1b
1036 #define RADEON_INFO_VCE_FB_VERSION	0x1c
1037 #define RADEON_INFO_NUM_BYTES_MOVED	0x1d
1038 #define RADEON_INFO_VRAM_USAGE		0x1e
1039 #define RADEON_INFO_GTT_USAGE		0x1f
1040 #define RADEON_INFO_ACTIVE_CU_COUNT	0x20
1041 #define RADEON_INFO_CURRENT_GPU_TEMP	0x21
1042 #define RADEON_INFO_CURRENT_GPU_SCLK	0x22
1043 #define RADEON_INFO_CURRENT_GPU_MCLK	0x23
1044 #define RADEON_INFO_READ_REG		0x24
1045 #define RADEON_INFO_VA_UNMAP_WORKING	0x25
1046 #define RADEON_INFO_GPU_RESET_COUNTER	0x26
1067 #define SI_TILE_MODE_DEPTH_STENCIL_2D		0