Lines Matching +full:highly +full:- +full:integrated
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
222 * IEEE 754-2008 binary16 half-precision float
232 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
248 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
252 * 16-xx padding occupy lsb
260 * 16-xx padding occupy lsb except Y410
285 * 1-plane YUV 4:2:0
288 * These formats can only be used with a non-Linear modifier.
318 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
319 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
327 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
364 /* 3 plane non-subsampled (444) YCbCr
372 /* 3 plane non-subsampled (444) YCrCb
397 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
398 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
404 * Format modifiers describe, typically, a re-ordering or modification
408 * The upper 8 bits of the format modifier are a vendor-id as assigned
427 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
447 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
449 * compatibility, in cases where a vendor-specific definition already exists and
454 * generic layouts (such as pixel re-ordering), which may have
455 * independently-developed support across multiple vendors.
458 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
485 * which tells the driver to also take driver-internal information into account
495 * used is out-of-band information carried in an API-specific way (e.g. in a
503 * Intel X-tiling layout
506 * in row-major layout. Within the tile bytes are laid out row-major, with
507 * a platform-dependent stride. On top of that the memory can apply
508 * platform-depending swizzling of some higher address bits into bit6.
511 * On earlier platforms the is highly platforms specific and not useful for
512 * cross-driver sharing. It exists since on a given platform it does uniquely
513 * identify the layout in a simple way for i915-specific userspace, which
520 * Intel Y-tiling layout
523 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
524 * chunks column-major, with a platform-dependent height. On top of that the
525 * memory can apply platform-depending swizzling of some higher address bits
529 * On earlier platforms the is highly platforms specific and not useful for
530 * cross-driver sharing. It exists since on a given platform it does uniquely
531 * identify the layout in a simple way for i915-specific userspace, which
538 * Intel Yf-tiling layout
540 * This is a tiled layout using 4Kb tiles in row-major layout.
541 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
542 * are arranged in four groups (two wide, two high) with column-major layout.
544 * out as 2x2 column-major.
556 * The main surface will be plane index 0 and must be Y/Yf-tiled,
573 * Intel color control surfaces (CCS) for Gen-12 render compression.
575 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
579 * Y-tile widths.
584 * Intel color control surfaces (CCS) for Gen-12 media compression
586 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
590 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
597 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
600 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
639 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
680 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
707 * on integrated graphics
709 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
721 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
731 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
733 * Macroblocks are laid in a Z-shape, and each pixel data is following the
738 * - multiple of 128 pixels for the width
739 * - multiple of 32 pixels for the height
741 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
746 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
748 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
758 * Implementation may be platform and base-format specific.
771 * Implementation may be platform and base-format specific.
784 * Implementation may be platform and base-format specific.
794 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
800 * Vivante 64x64 super-tiling layout
802 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
803 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
807 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
812 * Vivante 4x4 tiling layout for dual-pipe
816 * compared to the non-split tiled layout.
821 * Vivante 64x64 super-tiling layout for dual-pipe
823 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
825 * therefore halved compared to the non-split super-tiled layout.
830 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
882 * ---- ----- -----------------------------------------------------------------
886 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
888 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
890 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
892 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
900 * 11:9 - Reserved (To support 2D-array textures with variable array stride
921 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
922 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
932 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
948 * 55:25 - Reserved for future use. Must be zero.
960 * with block-linear layouts, is remapped within drivers to the value 0xfe,
961 * which corresponds to the "generic" kind used for simple single-sample
962 * uncompressed color formats on Fermi - Volta GPUs.
979 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1022 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1024 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1033 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1036 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1039 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1043 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1044 * tiles) or right-to-left (odd rows of 4k tiles).
1067 * and UV. Some SAND-using hardware stores UV in a separate tiled
1111 * the assumption is that a no-XOR tiling modifier will be created.
1119 * It provides fine-grained random access and minimizes the amount of data
1124 * and different devices or use-cases may support different combinations.
1156 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1173 * AFBC block-split
1194 * AFBC copy-block restrict
1196 * Buffers with this flag must obey the copy-block restriction. The restriction
1197 * is such that there are no copy-blocks referring across the border of 8x8
1217 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1223 * AFBC double-buffer
1225 * Indicates that the buffer is allocated in a layout safe for front-buffer
1233 * Indicates that the buffer includes per-superblock content hints.
1250 * Arm Fixed-Rate Compression (AFRC) modifiers
1254 * reductions in graphics and media use-cases.
1270 * ---------------- ---------------
1281 * ------ ----------------- ------------------
1290 * ----------------------------- --------- ----------------- ------------------
1293 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1294 * ----------------------------- --------- ----------------- ------------------
1297 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1298 * ----------------------------- --------- ----------------- ------------------
1300 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1301 * ----------------------------- --------- ----------------- ------------------
1304 * ----------------------------- --------- ----------------- ------------------
1323 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1328 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1330 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1332 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1346 * Indicates if the buffer uses the scanline-optimised layout
1347 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1353 * Arm 16x16 Block U-Interleaved modifier
1372 * both in row-major order.
1386 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1388 * - DRM_FORMAT_YUV420_8BIT
1389 * - DRM_FORMAT_YUV420_10BIT
1413 * - a body content organized in 64x32 superblocks with 4096 bytes per
1415 * - a 32 bytes per 128x64 header block
1433 * be accessible by the user-space clients, but only accessible by the
1436 * The user-space clients should expect a failure while trying to mmap
1437 * the DMA-BUF handle returned by the producer.
1462 * - main surface
1465 * - main surface in plane 0
1466 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1469 * - main surface in plane 0
1470 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1471 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1473 * For multi-plane formats the above surfaces get merged into one plane for
1477 * ----- ------------------------ ---------------------------------------------
1493 * 55:36 - Reserved for future use, must be zero
1513 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1525 * 0 - LINEAR
1526 * 1 - 256B_2D - 2D block dimensions
1527 * 2 - 4KB_2D
1528 * 3 - 64KB_2D
1529 * 4 - 256KB_2D
1530 * 5 - 4KB_3D - 3D block dimensions
1531 * 6 - 64KB_3D
1532 * 7 - 256KB_3D
1554 * one which is not-aligned.