uapi/drm/drm_fourcc.h

553  * Intel color control surface (CCS) for render compression
557  * the CCS will be plane index 1.
559  * Each CCS tile matches a 1024x512 pixel area of the main surface.
560  * To match certain aspects of the 3D hardware the CCS is
562  * the CCS pitch must be specified in multiples of 128 bytes.
564  * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
573  * Intel color control surfaces (CCS) for Gen-12 render compression.
575  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
576  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
577  * main surface. In other words, 4 bits in CCS map to a main surface cache
584  * Intel color control surfaces (CCS) for Gen-12 media compression
586  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
587  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
588  * main surface. In other words, 4 bits in CCS map to a main surface cache
590  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
592  * planes 2 and 3 for the respective CCS.
597  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
600  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
609  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
627  * Intel color control surfaces (CCS) for DG2 render compression.
629  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
631  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
637  * Intel color control surfaces (CCS) for DG2 media compression.
641  * 0 and 1, respectively. The CCS for all planes are stored outside of the
643  * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
649  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
651  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
653  * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
663  * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
665  * The main surface is tile4 and at plane index 0, the CCS is linear and
666  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
667  * main surface. In other words, 4 bits in CCS map to a main surface cache
674  * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
676  * The main surface is tile4 and at plane index 0, the CCS is linear and
677  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
678  * main surface. In other words, 4 bits in CCS map to a main surface cache
680  * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
682  * planes 2 and 3 for the respective CCS.
687  * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
690  * The main surface is tile4 and is at plane index 0 whereas CCS is linear
699  * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
706  * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
711  * 0 and 1, respectively. The CCS for all planes are stored outside of the
713  * CCS data for all compressible GEM objects.
718  * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
723  * 0 and 1, respectively. The CCS for all planes are stored outside of the
725  * CCS data for all compressible GEM objects. The GEM object must be stored in