Lines Matching +full:8 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
117 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
128 /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
129 #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
140 /* 8 bpp Red (direct relationship between channel value and brightness) */
141 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
153 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
154 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
160 /* 8 bpp RGB */
161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
214 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 littl…
215 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 littl…
217 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
218 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
228 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
229 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
235 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
238 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
239 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
240 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
241 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
243 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
244 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
245 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
246 #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endi…
247 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
262 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
263 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
264 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
268 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
272 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
274 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
276 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
288 * These formats can only be used with a non-Linear modifier.
290 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
294 * 2 plane RGB + A
296 * index 1 = A plane, [7:0] A
298 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
299 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
300 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
301 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
302 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
303 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
304 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
305 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
404 * Format modifiers describe, typically, a re-ordering or modification
405 * of the data in a plane of an FB. This can be used to express tiled/
406 * swizzled formats, or compression, or a combination of the two.
408 * The upper 8 bits of the format modifier are a vendor-id as assigned
441 * When adding a new token please document the layout with a code comment,
449 * compatibility, in cases where a vendor-specific definition already exists and
450 * a generic name for it is desired, the common name is a purely symbolic alias
457 * In future cases where a generic layout is identified before merging with a
458 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
461 * apply to a single vendor.
474 * This modifier can be used as a sentinel to terminate the format modifiers
475 * list, or to initialize a variable with an invalid modifier. It might also be
486 * and so might actually result in a tiled framebuffer.
495 * used is out-of-band information carried in an API-specific way (e.g. in a
505 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
507 * a platform-dependent stride. On top of that the memory can apply
510 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
512 * cross-driver sharing. It exists since on a given platform it does uniquely
513 * identify the layout in a simple way for i915-specific userspace, which
522 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
524 * chunks column-major, with a platform-dependent height. On top of that the
528 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
530 * cross-driver sharing. It exists since on a given platform it does uniquely
531 * identify the layout in a simple way for i915-specific userspace, which
540 * This is a tiled layout using 4Kb tiles in row-major layout.
546 * either a square block or a 2:1 unit.
555 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
559 * Each CCS tile matches a 1024x512 pixel area of the main surface.
564 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
565 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
576 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
577 * main surface. In other words, 4 bits in CCS map to a main surface cache
578 * line pair. The main surface pitch is required to be a multiple of four
587 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
588 * main surface. In other words, 4 bits in CCS map to a main surface cache
589 * line pair. The main surface pitch is required to be a multiple of four
609 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
611 * pitch is required to be a multiple of 4 tile widths.
613 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
621 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
622 * of 64B x 8 rows.
630 * outside of the GEM object in a reserved memory area dedicated for the
632 * main surface pitch is required to be a multiple of four Tile 4 widths.
642 * GEM object in a reserved memory area dedicated for the storage of the
644 * pitch is required to be a multiple of four Tile 4 widths.
652 * outside of the GEM object in a reserved memory area dedicated for the
654 * main surface pitch is required to be a multiple of four Tile 4 widths. The
666 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
667 * main surface. In other words, 4 bits in CCS map to a main surface cache
668 * line pair. The main surface pitch is required to be a multiple of four
677 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
678 * main surface. In other words, 4 bits in CCS map to a main surface cache
679 * line pair. The main surface pitch is required to be a multiple of four
699 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
701 * pitch is required to be a multiple of 4 tile widths.
712 * GEM object in a reserved memory area dedicated for the storage of the
724 * GEM object in a reserved memory area dedicated for the storage of the
726 * contiguous memory with a size aligned to 64KB
733 * Macroblocks are laid in a Z-shape, and each pixel data is following the
748 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
749 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
757 * Refers to a compressed variant of the base format that is compressed.
794 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
802 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
803 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
814 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
824 * starts at a different base address. Offsets from the base addresses are
831 * the color buffer tiling modifiers defined above. When TS is present it's a
836 * We reserve the top 8 bits of the Vivante modifier space for tile status
847 * Vivante compression modifiers. Those depend on a TS modifier being present
873 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
875 * a block depth or height of "4").
892 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
896 * hardware support a block width of two gobs, but it is impractical
904 * 19:12 k Page Kind. This value directly maps to a field in the page
917 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
921 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
923 * 2 = Gob Height 8, Turing+ Page Kind mapping
926 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
977 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
979 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1013 * type, and the next 24 bits for parameters. Top 8 bits are the
1016 #define __fourcc_mod_broadcom_param_shift 8
1033 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1036 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1039 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1067 * and UV. Some SAND-using hardware stores UV in a separate tiled
1073 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1110 * necessary to reduce the padding. If a hardware block can't do XOR,
1111 * the assumption is that a no-XOR tiling modifier will be created.
1118 * AFBC is a proprietary lossless image compression protocol and format.
1133 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1149 * size (in pixels) must be aligned to a multiple of the superblock size.
1176 * half of the payload is positioned at a predefined offset from the start
1184 * This flag indicates that the payload of each superblock must be stored at a
1197 * is such that there are no copy-blocks referring across the border of 8x8
1198 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1205 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1206 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1212 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1218 * can be reduced if a whole superblock is a single color.
1225 * Indicates that the buffer is allocated in a layout safe for front-buffer
1243 * affects the storage mode of the individual superblocks. Note that even a
1252 * AFRC is a proprietary fixed rate image compression protocol and format,
1260 * "coding unit" blocks which are individually compressed to a
1261 * fixed size (in bytes). All coding units within a given plane of a buffer
1276 * to a multiple of the paging tile dimensions.
1283 * ROT 8 coding units 8 coding units
1292 * Example: 16x4 luma samples in a 'Y' plane
1293 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1295 * 1 ROT 8 samples 8 samples
1296 * Example: 8x8 luma samples in a 'Y' plane
1297 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1299 * 2 DONT CARE 8 samples 4 samples
1300 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1350 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1366 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1379 * Amlogic uses a proprietary lossless image compression protocol and format
1386 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1391 * The first 8 bits of the mode defines the layout, then the following 8 bits
1398 #define __fourcc_mod_amlogic_options_shift 8
1413 * - a body content organized in 64x32 superblocks with 4096 bytes per
1415 * - a 32 bytes per 128x64 header block
1436 * The user-space clients should expect a failure while trying to mmap
1447 * boundaries, i.e. 8bit should be stored in this mode to save allocation
1480 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1545 #define AMD_FMT_MOD_TILE_SHIFT 8
1573 * and prefers the driver provided color. This necessitates doing a fastclear
1574 * eliminate operation before a process transfers control.